VHDL中的測試臺

Question

我設計了一個實體乘法和一個實現此實體的體系結構，但我不知道如何爲此編寫測試臺。換句話說：我如何將價值傳遞給我的架構？ 我不確定這段代碼是否正確，但我不能測試它，而不傳遞值。

library ieee; 
use ieee.numeric_std.all; 
use ieee.std_logic_1164.all; 

entity multiply is 
port (
    in_A : in std_ulogic_vector(7 downto 0); 
    in_B : in std_ulogic_vector(7 downto 0); 
    out_Q : out std_ulogic_vector(15 downto 0) 
); 
end multiply; 

architecture multiply_arch of multiply is 
signal p0 : std_ulogic_vector(7 downto 0); 
signal p1 : std_ulogic_vector(7 downto 0); 
signal p2 : std_ulogic_vector(7 downto 0); 
signal p3 : std_ulogic_vector(7 downto 0); 
signal p4 : std_ulogic_vector(7 downto 0); 
signal p5 : std_ulogic_vector(7 downto 0); 
signal p6 : std_ulogic_vector(7 downto 0); 
signal p7 : std_ulogic_vector(7 downto 0); 
begin 
p0 <= (7 downto 0 => in_A(0)) and in_B; 
p1 <= (7 downto 0 => in_A(1)) and in_B; 
p2 <= (7 downto 0 => in_A(2)) and in_B; 
p3 <= (7 downto 0 => in_A(3)) and in_B; 
p4 <= (7 downto 0 => in_A(4)) and in_B; 
p5 <= (7 downto 0 => in_A(5)) and in_B; 
p6 <= (7 downto 0 => in_A(6)) and in_B; 
p7 <= (7 downto 0 => in_A(7)) and in_B; 

out_Q(15 downto 1) <= std_ulogic_vector((unsigned(p0) + unsigned(p1&"0") + unsigned(p2&"00") + unsigned(p3&"000") + unsigned(p4&"0000") + unsigned(p5&"00000") + unsigned(p6&"000000") + unsigned(p7&"0000000"))); 
end architecture multiply_arch; 

Answer 1

您需要創建組件定義，然後在另一個文件中實例化該組件。該文件將成爲您的測試平臺文件。

測試臺文件將需要有component看起來像這樣：

component multiply is 
port (
    in_A : in std_ulogic_vector(7 downto 0); 
    in_B : in std_ulogic_vector(7 downto 0); 
    out_Q : out std_ulogic_vector(15 downto 0) 
); 
end component multiply; 

然後下面的begin聲明爲您architecture您需要的組件實例，這將是這個樣子：

multiply_inst : multiply 
port map (
    in_A => test_A, 
    in_B => test_B, 
    out_Q => test_out 
); 

您將需要從您的測試臺驅動信號test_A和test_B，並查看信號test_out的結果以查看您的乘法模塊是否按預期執行。

對於這個顯示的一個完整的例子：本multiply實體如何create a testbench in VHDL

Answer 2

具有很少的輸入位（僅16 std_logic）並且沒有 時鐘或狀態的模塊中，因此一個詳盡的測試臺，它試圖全部0/1 可以創建輸入的組合。該測試臺可以包括 「參考」模型，其在乘法運算的情況下簡單地是*。

一種用於這樣的測試臺的建議包含如下：

library ieee; 
use ieee.std_logic_1164.all; 

entity multiply_tb is 
end entity; 


library ieee; 
use ieee.numeric_std.all; 

architecture sim of multiply_tb is 

    signal dut_in_a : std_ulogic_vector(7 downto 0); 
    signal dut_in_b : std_ulogic_vector(7 downto 0); 
    signal dut_out_q : std_ulogic_vector(15 downto 0); 

    signal dut_ok : boolean; 

begin 

    -- Device Under Test (DUT) 
    multiply_e : entity work.multiply 
    port map(
     in_A => dut_in_a, 
     in_B => dut_in_b, 
     out_Q => dut_out_q); 

    -- Result generation 
    dut_ok <= to_integer(unsigned(dut_in_a)) * to_integer(unsigned(dut_in_b)) = 
      to_integer(unsigned(dut_out_q(15 downto 1))); 

    -- Stimuli generation and result test 
    process is 
    variable in_a_v : natural; 
    variable in_b_v : natural; 
    variable out_q_v : natural; 
    begin 
    for in_a_v in 0 to 255 loop 
     for in_b_v in 0 to 255 loop 
     dut_in_a <= std_ulogic_vector(to_unsigned(in_a_v, dut_in_a'length)); 
     dut_in_b <= std_ulogic_vector(to_unsigned(in_b_v, dut_in_b'length)); 
     wait for 5 ns; 
     assert dut_ok report "DUT failed" severity ERROR; 
     wait for 5 ns; 
     end loop; 
    end loop; 
    wait; -- End of simulation 
    end process; 

end architecture; 

注意，它看起來像有在multiply實體一些bug，因爲位0 的out_Q不被驅動，並且上的位不會產生適當的乘數 結果。如果問題得到解決，則應根據情況更新結果生成（參考模型） 。