2015-05-24 70 views
2


我想運行一個代碼,我已經在網上找到,但它不知何故測試臺無法在GHDL上運行預期的輸出。

VHDL時鐘測試臺

結構代碼 庫IEEE; 使用IEEE.STD_LOGIC_1164.ALL;

entity clk200Hz is 
    Port (
     clk_in : in STD_LOGIC; 
     reset : in STD_LOGIC; 
     clk_out: out STD_LOGIC 
    ); 
end clk200Hz; 

architecture Behavioral of clk200Hz is 
    signal temporal: STD_LOGIC; 
    signal counter : integer range 0 to 124999 := 0; 
begin 
    frequency_divider: process (reset, clk_in) begin 
     if (reset = '1') then 
      temporal <= '0'; 
      counter <= 0; 
     elsif rising_edge(clk_in) then 
      if (counter = 124999) then 
       temporal <= NOT(temporal); 
       counter <= 0; 
      else 
       counter <= counter + 1; 
      end if; 
     end if; 
    end process; 

    clk_out <= temporal; 
end Behavioral; 

試驗檯:

LIBRARY ieee; 
    USE ieee.std_logic_1164.ALL; 

    ENTITY clk200Hz_tb IS 
    END clk200Hz_tb; 

    ARCHITECTURE behavior OF clk200Hz_tb IS 
     COMPONENT clk200Hz 
     PORT(
     clk_in : IN std_logic; 
     reset : IN std_logic; 
     clk_out: OUT std_logic 
    ); 
     END COMPONENT; 

     -- Inputs 
     signal clk_in : std_logic := '0'; 
     signal reset : std_logic := '0'; 
     -- Outputs 
     signal clk_out : std_logic; 
     constant clk_in_t : time := 20 ns; 
    BEGIN 
     -- Instance of unit under test. 
     uut: clk200Hz PORT MAP (
     clk_in => clk_in, 
     reset => reset, 
     clk_out => clk_out 
    ); 

     -- Clock definition. 
     entrada_process :process 
     begin 
     clk_in <= '0'; 
     wait for clk_in_t/2; 
     clk_in <= '1'; 
     wait for clk_in_t/2; 
     end process; 

     -- Processing. 
     stimuli: process 
     begin 
     reset <= '1'; -- Initial conditions. 
     wait for 100 ns; 
     reset <= '0'; -- Down to work! 
      wait; 
     end process; 
    END; 

我期待有一個波,將形成一個時鐘脈衝上下,但是這似乎並沒有這樣的情況。我不知道設計有什麼問題。


我跑以下命令:

ghdl -s *.vhd 
    ghdl -a *.vhd 
    ghdl -e clk200Hz_tb 
    ghdl -r clk200Hz_tb --vcd=led.vcd 
    gtkwave led.vcd 

,這是我的輸出enter image description here
但時鐘了,我期待一個向上和向下的信號,而不是0

感謝的信號

+0

VHDL代碼看起來不錯,您使用的是什麼ghdl命令。你如何斷言有什麼問題? –

回答

0

我已經修復了這個問題,在我的運行命令中,我只是添加了ghdl -r clk200Hz_tb --vcd = led.vcd --stop-time = 100ns。

+0

這是在gtkwave屏幕截圖中顯示水平滾動條的好參數。 – user1155120

0

ghdl -a clk200Hz_tb.vhdl
ghdl -e clk200Hz_tb
ghdl -r clk200Hz_tb --wave = clk200hz_tb.ghw --stop時間= 500ns的

都給:

clk200hz_tb.png (可點擊)