VHDL測試平臺，真正的端口號

Question

內部系統的Verilog模型我有一個真正的輸入的SV子塊：

`include "Components.sv" 

    module EPO_REG #(parameter bit ExtIso = 1, real th_high = 5.5 , real th_low = 4.2)(input bit EPO_SETPOINT, NVC_PMOS_ON, NVC_NMOS_ON ,**input var real IVcc5, Viso, Vcc5_ext** ,output real EpoPower, Vcc5, IEPO); 

    real Iin; 
    real Vout; 
    real Vcap; 
    real Ids_nmos; 
    ........... 
    ........... 

我把這個塊的VHDL頂層（或測試平臺），例如以這種方式：

LIBRARY IEEE; 
USE IEEE.STD_LOGIC_1164.ALL; 
USE IEEE.NUMERIC_STD.ALL; 
USE IEEE.MATH_REAL.ALL; 

entity EPO_REG_WRAP is 

    GENERIC (
     ExtIso  : bit := '1'; 
     th_high : REAL := 5.5; 
     th_low  : REAL := 4.2 
    ); 
    PORT (
     NVC_PMOS_ON : IN STD_LOGIC; 
     NVC_NMOS_ON : IN STD_LOGIC; 
     EPO_SETPOINT : IN STD_LOGIC; 
     Vcc5_ext  : IN REAL; 
     IVcc5  : IN REAL; 
     Viso   : IN REAL; 
     Vcc5   : OUT REAL; 
     EpoPower  : OUT REAL; 
     IEPO   : OUT REAL 
    ); 
end; 

architecture beh of EPO_REG_WRAP is 

COMPONENT EPO_REG 
    GENERIC (
     ExtIso  : bit := '1'; 
     th_high : REAL := 5.5; 
     th_low  : REAL := 4.2 
    ); 
    PORT (
     NVC_PMOS_ON : IN STD_LOGIC; 
     NVC_NMOS_ON : IN STD_LOGIC; 
     EPO_SETPOINT : IN STD_LOGIC; 
     Vcc5_ext  : IN REAL; 
     IVcc5  : IN REAL; 
     Viso   : IN REAL; 
     Vcc5   : OUT REAL; 
     EpoPower  : OUT REAL; 
     IEPO   : OUT REAL 
    ); 
end component; 

begin 

UEPO_REG: EPO_REG 
     GENERIC MAP(
      ExtIso  => '1', 
      th_high => 5.5, 
      th_low => 4.2 
     ) 
     PORT MAP(
      NVC_PMOS_ON => NVC_PMOS_ON, 
      NVC_NMOS_ON => NVC_NMOS_ON, 
      EPO_SETPOINT => EPO_SETPOINT, 
      Vcc5_ext   => Vcc5_ext, 
      IVcc5 => IVCC5, 
      Viso => Viso, 
      EpoPower => EpoPower, 
      Vcc5 => Vcc5, 
      IEPO => IEPO 
     ); 

end; 

但我的闡述過程中得到以下錯誤：

ncelab: *E,MAINVR: Mapping of Verilog var port of mode IN with VHDL port/signal of entity/component 'VCC5_EXT' (File : EPO_REG_WRAP.vhd, line: 42, position: 13) is not supported. 
ncelab: *E,MAINVR: Mapping of Verilog var port of mode IN with VHDL port/signal of entity/component 'IVCC5' (File : EPO_REG_WRAP.vhd, line: 43, position: 10) is not supported. 
ncelab: *E,MAINVR: Mapping of Verilog var port of mode IN with VHDL port/signal of entity/component 'VISO' (File :EPO_REG_WRAP.vhd, line: 44, position: 9) is not supported. 

據我所知SV支持O實值n個端口。我做錯了什麼？

Answer 1

我通過從SV-2008切換到SV-2012解決了。

SV-2008不允許從真實網絡驅動，但它只能管理變量。 SV-2012允許管理信號。

Answer 2

我可以通過給予文件.sv擴展名來解析下面的罰款與Cadence（irun）Incisive 13.01當它被設置爲SystemVerilog。

module EPO_REG #(
    parameter bit ExtIso = 1, 
    real th_high = 5.5 , 
    real th_low = 4.2 
)(
    input bit EPO_SETPOINT, NVC_PMOS_ON, NVC_NMOS_ON , 
    input var real IVcc5, Viso, Vcc5_ext, 
    output real EpoPower, Vcc5, IEPO); 
endmodule