VHDL（Xilinx工具鏈）我正在被「陣列修剪」弄糟

我有一個兩個文件的VHDL項目，我有初學者的困難。VHDL（Xilinx工具鏈）我正在被「陣列修剪」弄糟

它需要系統時鐘並使用30位時鐘分頻器（其中我只使用少量非連續位）來驅動原始串行端口模塊（僅出局TX）模塊以便吐出8位字符定期。

看來，在合成過程中，許多重要的信號被優化器刪除，這是我沒想到的。

頂層文件「Glue.vhd」 ...

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all; 
use ieee.std_logic_unsigned.all; 

entity Glue is 
    port(
     clk : in std_logic; 
     tx : out std_logic; 
     LED : out std_logic_vector(1 downto 0) 
     ); 
end entity Glue; 

architecture behavioural of Glue is 
    signal divider : unsigned(29 downto 0); 
begin 
    LED(1) <= '0'; 

    ser_tx : entity SerialTX 
    port map (
      baud_clk => divider(12), 
      byte_to_transmit => std_ulogic_vector(divider(29 downto 22)), 
      poke => divider(20), 
      busy => LED(0), 
      serial_out => tx 
      ); 

    clocker : process(clk) 
    begin 
     IF(rising_edge(clk)) then 
      divider <= divider + 1; 
     END IF; 
    end process clocker; 
end architecture behavioural;

SerialTX.vhd

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.numeric_std.all; 

entity SerialTX is 
    port (
     baud_clk   : in std_logic; 
     byte_to_transmit : in std_ulogic_vector(7 downto 0); --the byte that we want to transmit 
     poke    : in std_logic;      --a rising edge causes the byte to be sent out 
     busy    : out std_logic;      --wait for this to go low before transmiting more data 
     serial_out  : out std_logic      --the RS232 serial signal 
     ); 
end SerialTX; 

architecture behavioural of SerialTX is 
    signal bit_buf    : unsigned(9 downto 0); --(STOP bit) & (8 data bits) & (START bit) 
    signal internal_busy   : std_logic; 
    shared variable bit_counter : integer range 0 to 10; 
begin 
    busy <= internal_busy; 

    busy_handler : process(poke) is 
    begin 
     if(rising_edge(poke)) then 
      internal_busy <= '1'; 
     end if; 
     if(bit_counter = 0) then 
      internal_busy <= '0'; 
     end if; 
    end process busy_handler; 

    do_transmit : process(baud_clk) is 
    begin 
     if(rising_edge(baud_clk)) then 
      if((internal_busy = '1') and (bit_counter = 0)) then 
       bit_counter := 10; 
       bit_buf <= unsigned('1' & byte_to_transmit & '0'); 
      end if; 

      serial_out <= bit_buf(0); 
      bit_buf <= bit_buf srl 1; 
      bit_counter := bit_counter - 1; 
     end if; 
    end process do_transmit; 
end behavioural;

的警告（沒有錯誤介意你）從合成過程如下...

WARNING:Xst:647 - Input <byte_to_transmit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. 
WARNING:Xst:1710 - FF/Latch <bit_buf_9> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_8> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_7> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_6> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_5> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_4> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_3> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_2> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_1> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_0> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <serial_out> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:2404 - FFs/Latches <bit_buf<9:0>> (without init value) have a constant value of 0 in block <SerialTX>. 
WARNING:Xst:1710 - FF/Latch <serial_out> (without init value) has a constant value of 0 in block <SerialTX>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:2677 - Node <divider_21> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_22> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_23> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_24> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_25> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_26> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_27> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_28> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_29> of sequential type is unconnected in block <Glue>. 
WARNING:Route:455 - CLK Net:divider<20> may have excessive skew because  0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. 
WARNING:Route:455 - CLK Net:divider<12> may have excessive skew because  0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

我已經追蹤了源代碼中的連接，並且找不到我所犯的錯誤。我感覺我錯過了一些我沒有在作業中提到過的邊緣/角落案例。

標記爲「（沒有初始值）」的項目我試圖通過給它們默認值進行糾正而無濟於事。被標記爲「不連接在塊中」的令人眼花繚亂。

我該怎麼做才能滿足合成器？

來源

2017-04-25 Wossname

它修剪你不使用的位。所以有什麼問題？它會在模擬中做同樣的事情，它在那裏正常工作，對吧？ –

@BrianDrummond，這是一個很好的問題。一旦我找出如何做到這一點，我會回答。 :) – Wossname

您的Glue缺少ser_tex組件實例中實體SerialTX的可見性。它不是直接可見的。經典的治療方法是使SerialTX在這裏顯示，並帶有一個選定的名稱「實體work.SerialTX - 添加工作前綴以選擇名稱」。這應該顯示在未顯示的早期警告中。如果沒有SerialTX綁定，只有驅動它的東西纔會被刪除。 Brian並沒有如此微妙的挖掘，合成器通常希望向他們展示功能代碼。保存一些額外的括號，你永遠不知道什麼時候你真的需要它們。 – user1155120

您可以模擬您的設計，它處於複雜性的邊緣，比在FPGA中合成並加載時更難以猜測它爲什麼不起作用。它也可以做成simpler。

有可能擺脫bit_counter，因爲你有一個10位的bit_buf移位寄存器。

這樣做的方法是設置一個默認模式，該模式被識別爲'空'，並且該模式是由於將bit_buf移出而創建的。

該模式不會發生，而不是作爲「0」中的「左移」移出的人工產物。移位寄存器移入「0」，並在停止位位於最右側位置時停止（「0000000001」）。右邊的'1'有位置保持發送空閒標記。

空閒模式的想法來自於您使用srl，它留下填充'0'，在調試您的原始設計時注意到。在「學習」的過程中，增量變化的數量爲什麼按照你所設計的方式進行設計變得令人望而卻步。它導致從最初的原則和基於你的實現來描述實現。

要模擬您的設計，首先要對Glue進行更改，包括分割的初始值，以便增量起作用，並將分隔器分支移出以進行戳和byte_to_transmit，以將仿真時間減少到40 ms爲以下。

SerialTx的實例化使用選定的名稱，模擬器隱式地不包括use work.all;上下文項，正如有時在綜合工具中提供的那樣。

的標記你的設計與添加的測試平臺，無bit_counter：

library ieee; 
use ieee.std_logic_1164.all; 
-- use ieee.numeric_std.all; 

entity SerialTX is 
    port (
     baud_clk:   in std_logic; 
     byte_to_transmit: in std_logic_vector(7 downto 0); -- before -2008 
     poke:    in std_logic; 
     busy:    out std_logic; 
     serial_out:  out std_logic 
    ); 
end entity SerialTX; 

architecture foo of SerialTX is 
    -- signal bit_buf:   unsigned(9 downto 0); 
    constant BB_IDLE:  std_logic_vector (9 downto 0) := "0000000001"; 
    signal bit_buf:   std_logic_vector (9 downto 0) := BB_IDLE; 
    -- signal internal_busy: std_logic; 
    signal poke_reg:  std_logic_vector (0 to 2) := "000"; 
    signal start_tx:  std_logic; 

    -- shared variable bit_counter: integer range 0 to 10; 
begin 
    -- busy <= internal_busy; 
poke_filt: 
    process (baud_clk) -- translate poke to baud_clk domain 
    begin 
     if rising_edge (baud_clk) then 
      poke_reg <= poke & poke_reg (0 to 1); 
     end if; 
    end process; 

    -- front edge of poke in baud_clk_domain: 
    start_tx <= poke_reg(0) and poke_reg(1) and not poke_reg(2); 

-- busy_handler: 
--  process (poke) is 
--  begin 
--   if rising_edge (poke) then 
--    internal_busy <= '1'; 
--   end if; 
--   if bit_counter = 0 then 
--    internal_busy <= '0'; 
--   end if; 
--  end process busy_handler; 

busy_handler: 
    process (baud_clk) 
    begin 
     if rising_edge (baud_clk) then 
      if start_tx = '1' and bit_buf = BB_IDLE then 
       busy <= '1'; 
      elsif bit_buf = BB_IDLE then 
       busy <= '0'; 
      end if; 
     end if; 
    end process; 

do_transmit: 
    process (baud_clk) 
    begin 
     if rising_edge(baud_clk) then 
      if start_tx = '1' and bit_buf = BB_IDLE then 
       bit_buf <= '1' & byte_to_transmit & '0'; 
      elsif bit_buf /= BB_IDLE then 
       -- bit_buf <= bit_buf srl 1; 
       -- srl UNDEFINED in package std_logic_1164 
       bit_buf <= '0' & bit_buf(9 downto 1); -- shift right one 
      end if;         -- zero fill 
     end if; 
    end process; 

-- do_transmit: 
--  process (baud_clk) 
--  begin 
--   if rising_edge(baud_clk) then 
--    if internal_busy = '1' and bit_counter = 0 then 
--     bit_counter := 10; 
--     bit_buf <= unsigned ('1' & byte_to_transmit & '0'); 
--    end if; 
--    serial_out <= bit_buf(0); 
--    bit_buf <= bit_buf srl 1; 
--    bit_counter := bit_counter - 1; 
--   end if; 
--  end process do_transmit; 

    serial_out <= bit_buf(0); -- ADDED, no 11th flip flop 

end architecture; 

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 
-- use ieee.std_logic_unsigned.all; 

entity Glue is 
    port (
     clk: in std_logic; 
     tx: out std_logic; 
     LED: out std_logic_vector(1 downto 0) 
    ); 
end entity Glue; 

architecture behavioural of Glue is 
    signal divider: unsigned(29 downto 0) := (others => '0'); -- init val 
begin 
    LED(1) <= '0'; 

ser_tx: 
    entity work.SerialTX -- ADDED work prefix to make selected name 
     port map (
      baud_clk => divider(12), 
     -- byte_to_transmit => std_ulogic_vector(divider(29 downto 22)), 
      byte_to_transmit => std_logic_vector(divider(25 downto 18)), 
      poke => divider(17), -- WAS divider(20), for simulation 
      busy => LED(0), 
      serial_out => tx 
     ); 
clocker: 
    process (clk) 
    begin 
     if rising_edge(clk) then 
      divider <= divider + 1; 
     end if; 
    end process clocker; 
end architecture behavioural; 

library ieee; 
use ieee.std_logic_1164.all; 

entity glue_tb is 
end entity; 

architecture fum of glue_tb is 
    signal clk:  std_logic := '0'; 
    signal tx:  std_logic; 
    signal led:  std_logic_vector(1 downto 0); 
begin 
DUT: 
    entity work.glue 
     port map (
      clk => clk, 
      tx => tx, 
      led => led 
     ); 
CLOCK: 
    process 
    begin 
     wait for 10 ns; 
     clk <= not clk; 
     if now > 40 ms then 
      wait; 
     end if; 
    end process; 
end architecture;

運行40毫秒，得出：

特寫byte_to_transmit值05：

你可能注意到srl沒有在包std_logic_1164中提供，並且由於使用了std_ulogic_vector而被替換了，std_logic_vector在-2008變成了它的子類型。

poke被過濾到baud_clk域併產生單個時鐘週期事件集合internal_busy爲「1」，當在bit_buf再次檢測空閒模式，其隨後設置爲「0」。

注意busy對於10個時鐘（起始位，8個數據位和停止位）爲'1'，串行輸出的第11個觸發器已被丟棄。

這是模擬使用ghdl，二進制文件可以下載here。波形顯示從gtkwave。兩者均獲得GPL許可。

VHDL具有一組特定的語言結構，用於推斷順序邏輯 - 存儲器，寄存器和鎖存器，這是合成中有用的語言子集的一部分。合格VHDL的超集或子集通常由綜合供應商支持，綜合供應商可能還包括基於其目標平臺芯片的限制。合格供應商文檔中提供了資格和支持的結構。 VHDL語言本身在IEEE Std 1076-2008中定義，但通用支持僅適用於-1993或-2002版本。

你會發現共享變量已成爲通過方法訪問的受保護類型，確保對共享資源的獨佔訪問，並且偶然地變得不適合合成。

我是正確的思維，你的3位poke_reg制度是指戳高脈衝持續時間必須長於3個階baud_clk邊緣正確檢測？是否有可能使捅信號邊沿觸發？ - Wossname 11小時以前

scary_jeff 's method將爲捅工作（發送）事件小於或等於三個baud_clk間隔。

您不使用SerialTx中的busy（internal_busy），它僅在實際傳輸期間覆蓋baud_clk週期（bauds）的間隔。

它可以創建一個繁忙的信號是安全的（雙翻蓋的XOR觸發器），並適用於捅（發送）的上升沿之間的整個時段和internal_busy結束：

architecture fum of SerialTX is 
    constant BB_IDLE:  std_logic_vector (9 downto 0) := "0000000001"; 
    signal bit_buf:   std_logic_vector (9 downto 0) := BB_IDLE; 
    signal poke_event:  std_logic := '0'; -- Added 
    signal internal_busy: std_logic := '0'; -- Re-Added 
    signal poke_reg:  std_logic_vector (0 to 1) := "00"; 
    signal start_tx:  std_logic; 
    signal end_event:  std_logic := '0'; -- Added 
begin 

    busy <= poke_event xor end_event; -- ADDED, was FF output 

pokeevent: 
    process (poke) 
    begin 
     if rising_edge(poke) then 
      poke_event <= not poke_event; 
     end if; 
    end process; 
poke_edge: 
    process (baud_clk) -- translate poke to baud_clk domain 
    begin 
     if rising_edge (baud_clk) then 
      poke_reg <= poke_event & poke_reg (0); 
     end if; 
    end process; 

    -- front edge of poke in baud_clk_domain: 
    start_tx <= poke_reg(0) xor poke_reg(1); -- CHANGED, when not equal 

endevent: 
    process (baud_clk) 
    begin 
     if rising_edge (baud_clk) then 
      if internal_busy = '1' and bit_buf = BB_IDLE then 
       end_event <= not end_event; 
      end if; 
     end if; 
    end process; 

busy_handler: -- CHANGED 
    process (baud_clk) 
    begin 
     if rising_edge (baud_clk) then 
      if start_tx = '1' and bit_buf = BB_IDLE then 
       internal_busy <= '1'; 
      elsif bit_buf = BB_IDLE then 
       internal_busy <= '0'; 
      end if; 
     end if; 
    end process; 

do_transmit: 
    process (baud_clk) 
    begin 
     if rising_edge(baud_clk) then 
      if start_tx = '1' and bit_buf = BB_IDLE then 
       bit_buf <= '1' & byte_to_transmit & '0'; 
      elsif bit_buf /= BB_IDLE then 
       bit_buf <= '0' & bit_buf(9 downto 1); 
      end if; 
     end if; 
    end process; 

    serial_out <= bit_buf(0); 

end architecture;

這給出：

注意，internal_busy信號被用來確定何時忙碌後邊緣發生時（發送或不當bit_buf空閒模式之間進行區分）。

的戳信號已經通過修飾膠證明戳的寬度縮短（發送）可以是任意的：

architecture behavioural of Glue is 
    signal divider: unsigned(29 downto 0) := (others => '0'); -- init val 
    signal poke: std_logic := '0'; -- ADDED 
begin 
    LED(1) <= '0'; 

    poke <= divider(17), '0' after 10 us; -- ADDED 
ser_tx: 
    entity work.SerialTX -- ADDED work prefix to make selected name 
     port map (
      baud_clk => divider(12), 
      -- byte_to_transmit => std_ulogic_vector(divider(29 downto 22)), 
      byte_to_transmit => std_logic_vector(divider(25 downto 18)),-- sim 
      poke => poke, -- WAS divider(20), for simulation 
      busy => LED(0), 
      serial_out => tx 
     );

（否，較新的信號戳一個singleshot該複雜波形是不能合成合格。）

來源

2017-04-26 23:27:22 user1155120

我會嘗試GHDL，謝謝你的提示。 – Wossname

我是否正確地認爲你的3位poke_reg系統意味着高脈衝持續時間必須長於3個baud_clk邊緣才能正確檢測？是否有可能使捅信號邊沿觸發？ – Wossname

我很確定我的方法適用於任何長度的'發送'脈衝到寄存器的最小時鐘脈衝寬度。如果不是，爲什麼？ –

雖然user1155120是正確的，你要麼指定庫或做組件綁定的感覺，你的工具很顯然是找到了正確的實體，因爲這是你的邏輯被優化。第一

第一件事，不要使用

use IEEE.numeric_std.all; 
use ieee.std_logic_unsigned.all;

在一起。除了使用遺留代碼時，您應該使用numeric_std。

真正的問題是雙重的：

你不初始化計數器變量，並沒有算對。
你的輸入數據永遠不會進入並行加載移位寄存器，因此被修剪。

你想讓你的櫃檯開始價值多少？ IIRC，未初始化的整數類型將假定其範圍內的最低有效值。不過，最好在任何情況下明確開始。然而，事實上FPGA中沒有整數 - 只是冷卻，硬的觸發器。 0到10的範圍至少使用4位，因此使用4個觸發器。然而，從0到「-1」將下溢並且回到15而不是你可能期望的10。 internal_busy旨在成爲觸發器，但未初始化。我說有意，因爲它實際上是由bit_counter異步復位。這種異步復位本身是有問題的，幾乎肯定不是你想要的：

busy_handler : process(poke) is -- <-- wrong sensitivity list 
begin 
    if(rising_edge(poke)) then 
     internal_busy <= '1'; 
    end if; 
    if(bit_counter = 0) then -- <-- not clocked 
     internal_busy <= '0'; 
    end if; 
end process busy_handler;

你混合了時鐘和組合代碼。你的模擬將被關閉，因爲同時internal_busy的安定將在硬件的同時，你的模擬工具將只顯示對poke變化更新。

-- can never happen, because bit_counter = 0 means internal_busy is forced to '0' 
if((internal_busy = '1') and (bit_counter = 0)) then 
    bit_counter := 10; 
    bit_buf <= unsigned('1' & byte_to_transmit & '0'); 
end if;

如果沒有這個邏輯，bit_buf的確會9'h000（值賽靈思工具假定 - 你沒有給任何一個！）。這是以下行試圖告訴你：

WARNING:Xst:1710 - FF/Latch <bit_buf_9> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_8> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_7> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_6> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_5> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_4> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_3> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_2> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_1> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1895 - Due to other FF/Latch trimming, FF/Latch <bit_buf_0> (without init value) has a constant value of 0 in block <ser_tx>. This FF/Latch will be trimmed during the optimization process. 
WARNING:Xst:1710 - FF/Latch <serial_out> (without init value) has a constant value of 0 in block <SerialTX>. This FF/Latch will be trimmed during the optimization process.

bit_buf_9恆定爲零，並用硬零（邏輯或織物）所取代。因此它的觸發器是多餘的，可以修剪。
bit_buf_{8..0}被確定爲等效於某些其他觸發器（這裏：bit_buf_9）。但是，該觸發器被修剪，因此，這些觸發器也將被修剪。
bit_buf_9飼料serial_out，所以它也被修剪。

錯誤消息的其餘部分：

WARNING:Xst:647 - Input <byte_to_transmit> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. 
WARNING:Xst:2677 - Node <divider_21> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_22> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_23> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_24> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_25> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_26> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_27> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_28> of sequential type is unconnected in block <Glue>. 
WARNING:Xst:2677 - Node <divider_29> of sequential type is unconnected in block <Glue>.

byte_to_transmit是未使用的，而不是頂級塊的一部分，它不會被保留。
divider(29 downto 22)連接到byte_to_transmit。由於該端口將被刪除，所有翻轉觸發器繼上次使用的觸發器，divider(20)可以被優化掉。

時鐘警告：

WARNING:Route:455 - CLK Net:divider<20> may have excessive skew because  0 CLK pins and 1 NON_CLK pins failed to route using a CLK template. 
WARNING:Route:455 - CLK Net:divider<12> may have excessive skew because  0 CLK pins and 1 NON_CLK pins failed to route using a CLK template.

divider(20)和divider(12)作爲時鐘。
divider(20)和divider(12)是從一個或多個切片內的邏輯：LUT和觸發器產生的。取決於FPGA，有一些可以反饋到時鐘佈線資源。
就你而言，這些工具沒有找到在時鐘路由資源上路由這些信號的方法，並且必須使用通常爲邏輯信號保留的資源，因此時滯可能過大。可以通過使用1.使用poke和baud_clk公共時鐘clk兩個模塊和2避免

這些時鐘誤差爲時鐘使能代替：

clk_en_p: process (clk) is 
begin 

if (rising_edge(clk)) then 
    if (clk_en = '1') then 
     my_signal <= assignment; 
    end if; 
end if; 
end process clk_en_p;

總而言之，你應該寫一測試平臺，並在Brian Drummond建議的綜合之前模擬您的設計。

在編寫實現之前編寫測試平臺的部分內容通常會很有幫助，因爲這會迫使您考慮組件的接口以及您希望在實際編寫之前做出反應。

來源

2017-04-26 00:56:30 FRob

我需要回到基本原則，並重新開始，到目前爲止，我完全誤解了這種語言。感謝您對郵件的詳細分類。 – Wossname

VHDL（Xilinx工具鏈）我正在被「陣列修剪」弄糟

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