VHDL代碼錯誤：「錯誤（10818）：無法推斷<name>在<location>的寄存器，因爲它不保留其時間邊緣以外的值」

Question

我知道這個錯誤已經遇到好幾次了，但作爲一個初學者我仍然無法看到如何在我自己的代碼中解決這個錯誤。錯誤和代碼都打印在下面，感謝任何人的輸入。

Error (10818): Can't infer register for count[0] at 5bit_PHreg_vhdl.vhd(21) because it does not hold its value outside the clock edge

對'count'的每一位重複出錯，並引用代碼中提到的行。

ARCHITECTURE behavioral OF 5bit_PHreg_vhdl IS 
SIGNAL count : STD_LOGIC_VECTOR(4 DOWNTO 0); 

BEGIN 
    PROCESS(reset, clk, SHR_EN) 
     BEGIN 
-- Check if asynchronous reset is 0 
     IF reset = '0' THEN --ERROR OCCURS HERE 
       count <= "00000"; 
-- Check if rising edge 
     ELSIF (clk'EVENT AND clk = '1') THEN 
       IF LD_EN = '1' THEN 
        count <= FA_in; 
       END IF; 
-- Check if SHR_EN is active 
     ELSIF (SHR_EN = '1') THEN 
       count(4) <= c_in; 
       count(3) <= count(4); 
       count(2) <= count(3); 
       count(1) <= count(2); 
       count(0) <= count(1); 
       c_out <= count(0); 
     END IF; 
    END PROCESS; 
    PH_reg_out <= count; 
END behavioral; 

Answer 1

ELSIF (SHR_EN = '1') THEN在復位和時鐘邊沿條件之外，它的形式不被識別用於合成。

如果它已註冊，則將其移動到前一端內的以下分配中。從進程敏感性列表中刪除SHR_EN。

同樣在VHDL中，名稱不能以數字開頭，5bit_PHreg_vhdl作爲實體名稱無效。

修復這些在缺少實體聲明填充：

library ieee; 
use ieee.std_logic_1164.all; 

entity PH_reg_5_bit is 
    port (
     reset:  in std_logic; 
     clk:  in std_logic; 
     LD_EN:  in std_logic; 
     SHR_EN:  in std_logic; 
     FA_in:  in std_logic_vector (4 downto 0); 
     c_in:  in std_logic; 
     c_out:  out std_logic; 
     PH_reg_out: out std_logic_vector (4 downto 0) 
    ); 
end entity; 

ARCHITECTURE behavioral OF PH_reg_5_bit IS 
    SIGNAL count : STD_LOGIC_VECTOR(4 DOWNTO 0); 

BEGIN 
    PROCESS (reset, clk) -- , SHR_EN) 
     BEGIN 
-- Check if asynchronous reset is 0 
     IF reset = '0' THEN --ERROR OCCURS HERE 
       count <= "00000"; 
-- Check if rising edge 
     ELSIF (clk'EVENT AND clk = '1') THEN 
       IF LD_EN = '1' THEN 
        count <= FA_in; 
     -- Check if SHR_EN is active 
       ELSIF (SHR_EN = '1') THEN 
         count(4) <= c_in; 
         count(3) <= count(4); 
         count(2) <= count(3); 
         count(1) <= count(2); 
         count(0) <= count(1); 
       END IF; 
-- -- Check if SHR_EN is active 
--   ELSIF (SHR_EN = '1') THEN 
--     count(4) <= c_in; 
--     count(3) <= count(4); 
--     count(2) <= count(3); 
--     count(1) <= count(2); 
--     count(0) <= count(1); 
--     c_out <= count(0); 
     END IF; 
    END PROCESS; 

    c_out <= count(0); -- c_out not separately registered 
    PH_reg_out <= count; 
END behavioral; 

和你的代碼成功分析。

實體名稱是一個很好的指示，你沒有模擬你的設計。

注意條件的順序意味着加載優先於移位。

我懷疑c_out不應該註冊，允許移位寄存器實例使用c_in和c_out連接到更大的移位寄存器。這意味着它的賦值應該在包含時鐘邊沿事件的if語句之外，它可以放在其他輸出引腳分配旁邊。