Vhdl的新功能,我試圖做一個6至64解碼器。我有一個正在運行的3到8位解碼器,我需要使用它(其中9個是精確的),使得6到64.我不斷得到10500的錯誤代碼,我聲明瞭組件的端口映射和「 ;」在行末。VHDL錯誤代碼10500
library ieee;
Use ieee.std_logic_1164.all;
entity dec6to64 is
port (w0,w1,w2,w3,w4,w5, En : in std_logic;
f : out std_logic_vector(63 downto 0));
end dec6to64;
Architecture Structure of dec6to64 is
component dec3to8
port(
w0,w1,w2, En : in std_logic;
y0,y1, y2, y3, y4, y5, y6 ,y7 : out std_logic);
end component;
Begin
process(w0, w1, w2, w3, w4, w5, En)
Begin
dec1: dec3to8 port map(w0, w1, w2, En, y0, y1, y2, y3, y4, y5, y6, y7);
dec2: dec3to8 port map(w3, w4, w5, y0, f(0), f(1), f(2), f(3), f(4), f(5), f(6), f(7));
dec3: dec3to8 port map(w3, w4, w5, y1, f(8), f(9), f(10), f(11), f(12), f(13), f(14), f(15));
dec4: dec3to8 port map(w3, w4, w5, y2, f(16), f(17), f(18), f(19), f(20), f(21), f(22), f(23));
dec5: dec3to8 port map(w3, w4, w5, y3, f(24), f(25), f(26), f(27), f(28), f(29), f(30), f(31));
dec6: dec3to8 port map(w3, w4, w5, y4, f(32), f(33), f(34), f(35), f(36), f(37), f(38), f(39));
dec7: dec3to8 port map(w3, w4, w5, y5, f(40), f(41), f(42), f(43), f(44), f(45), f(46), f(47));
dec8: dec3to8 port map(w3, w4, w5, y6, f(48), f(49), f(50), f(51), f(52), f(53), f(54), f(55));
dec9: dec3to8 port map(w3, w4, w5, y7, f(56), f(57), f(58), f(59), f(60), f(61), f(62), f(63));
end process;
end Structure;
你不提供足夠的代碼,以確定原因。它可能就像在構件實例化之前定義架構體的缺少begin語句一樣簡單。這不是[最小,完整和可驗證示例](http://stackoverflow.com/help/mcve)。 – user1155120
一個問題:組件有y1 .. y7,但實例有y0 .. y7,所以至少必須糾正。 –
修復了組件聲明。儘管如此,仍然有相同的錯誤。 – RabidRager