Verilog仿真給出了x作爲輸出

Question

我試圖用veriwell來模擬下面的電路。然而，仿真結果給了我每個網絡的價值爲x。由於電路沒有任何後向環路，我猜每個網絡應該有1或0信號。

module dff (CK,Q,D); 
input CK,D; 
output Q; 

    wire NM,NCK; 
    wire NQ,M; 

    nmos N7 (M,D,NCK); 
    not P3 (NM,M); 
    nmos N9 (NQ,NM,CK); 
    not P5 (Q,NQ); 
    not P1 (NCK,CK); 

endmodule 

module s27(clk, in1, in2, GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2); 
input clk, in1, in2; 
output GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2; 
wire AO, BO, CO, DO, EO, FO; 
wire a1, a2, a3, a4; 
wire o1, o2; 

    dff A(clk,AO,in1); 
    dff B(clk,BO,in2); 
    dff C(clk,CO,o1); 
    dff D(clk,DO,a1); 
    dff E(clk,EO,a2); 
    dff F(clk,FO,o2); 
    dff G(clk,GO,a3); 
    dff H(clk,HO,a4); 

    and AND2_1 (a1, AO, CO); 
    and AND2_2 (a2, CO, BO); 
    and AND2_3 (a3, AO, FO); 
    and AND2_4 (a4, FO, BO); 

    or OR2_1(o1, AO, BO); 
    or OR2_2(o2, DO, EO); 
endmodule 

我使用下面的測試平臺（使用腳本生成的）：

`timescale 1ns/1ps 

module testbench; 

parameter sOutFileName = "beSimOut.txt"; 
parameter nVectorWidth = 3; 
parameter nVectorSpace = 1000; 
parameter nSimCycle = 10; 

/* simulation memory */ 
reg [nVectorWidth - 1:0] mSimMemory [nVectorSpace - 1:0]; 

/* simulation vector */ 
reg [nVectorWidth - 1:0] vSimVector; 

/* bench variables */ 
integer nOutFile, nIndex; 

/* connection variable declarations */ 
wire clk, in1, in2, G0, H0, A0, B0, C0, D0, E0, F0, a1, a2, a3, a4, o1, o2; 
/* drive inputs */ 
assign clk = vSimVector[2]; 
assign in1 = vSimVector[1]; 
assign in2 = vSimVector[0]; 

/* simulation memory population routine */ 
task populateSimulationMemory; 
begin 
    for (nIndex = 0; nIndex < nVectorSpace; nIndex = nIndex + 1) 
     mSimMemory[nIndex] = { $random }; 
end 
endtask 

/* simulation */ 
initial 
begin 
    /* start monitoring */ 
    $monitor($time, ": clk = %b, in1 = %b, in2 = %b, GO = %b, HO = %b, AO = %b, BO = %b, CO = %b, DO = %b, EO = %b, FO = %b, a1 = %b, a2 = %b, a3 = %b, a4 = %b, o1 = %b, o2 = %b", clk, in1, in2, GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2); 

    /* populate simulation memory */ 
    populateSimulationMemory; 

    /* open dump file */ 
    nOutFile = $fopen(sOutFileName); 
    if (nOutFile == 0) 
    begin 
     $display("Can't open %s file for dumping. Exiting ...", sOutFileName); 
     $finish; 
    end 

    /* simulate inputs */ 
    for (nIndex = 0; nIndex < nVectorSpace; nIndex = nIndex + 1) 
     #nSimCycle vSimVector = mSimMemory[nIndex]; 

    #1 $fclose(nOutFile); 
    nOutFile = 0; 
    $finish; 
end 

/* instantiation */ 
s27 inst (.clk(clk), .in1(in1), .in2(in2), .GO(GO), .HO(HO), .AO(AO), .BO(BO), .CO(CO), .DO(DO), .EO(EO), .FO(FO), .a1(a1), .a2(a2), .a3(a3), .a4(a4), .o1(o1), .o2(o2)); 

/* dump */ 
always @(clk or in1 or in2 or GO or HO or AO or BO or CO or DO or EO or FO or a1 or a2 or a3 or a4 or o1 or o2) 
    if (nOutFile != 0) 
     $fdisplay(nOutFile, $time, ": clk = %b, in1 = %b, in2 = %b, GO = %b, HO = %b, AO = %b, BO = %b, CO = %b, DO = %b, EO = %b, FO = %b, a1 = %b, a2 = %b, a3 = %b, a4 = %b, o1 = %b, o2 = %b", clk, in1, in2, GO, HO, AO, BO, CO, DO, EO, FO, a1, a2, a3, a4, o1, o2); 

endmodule 

爲什麼我沒有得到正確的輸出任何想法？

在此先感謝。

Answer 1

該dff沒有正確建模。在當前dff的情況下，當CK高時，M將浮動（高Z）。

DFF應該是這樣的：

not N1 (NCK,CK); 
cmos C1 (M,D,NCK,CK); 
cmos C2 (M,NNM,CK,NCK); 
not N2 (NM,M); 
not N3 (NNM,NM); 
cmos C3 (NNQ,NNM,CK,NCK); 
cmos C4 (NNQ,Q,NCK,CK); 
not N3 (NQ,NNQ); 
not N4 (Q,NQ); 

或與非門：

nand DN1 (NM,D,CK); 
nand DN2 (M,NM,CK); 
nand DN3 (Q,NQ,NM); 
nand ND4 (QN,Q,M); 

或行爲：

always @(posedge CK) 
    Q <= D; 

Answer 2

當我嘗試使用VCS模擬器編譯代碼時，我得到一個編譯錯誤：

Identifier 'GO' has not been declared yet. If this error is not expected, please check if you have set `default_nettype to none.

在您的測試平臺模塊，可以聲明導線G0（數字零），但你使用GO （大寫字母O）。你應該改變零字母O的。

我不認爲這會完全解決您的問題，但這太複雜，不適合評論。