VHDL Testbench代碼不適用於寄存器

我想模擬寄存器邏輯，但測試臺不工作，當影響輸入信號「Si，ECi，Ri，Ci」時，所有信號輸入固定爲「 0000000001「當我在Xlinix中運行模擬時，輸出固定爲」ZZZZZZZZ0「我不知道爲什麼？VHDL Testbench代碼不適用於寄存器

這裏的寄存器的代碼VHDL

library IEEE; 
use IEEE.std_logic_1164.all; 
use IEEE.std_logic_arith.all; 
use IEEE.std_logic_unsigned.all; 
use IEEE.numeric_std.all; 

entity Registre is 
    Generic (N: positive :=10); 
    Port (R : in STD_LOGIC_VECTOR (N downto 1); 
      EC : in STD_LOGIC_VECTOR (N downto 1); 
      C : in STD_LOGIC_VECTOR (N downto 1); 
      S : in STD_LOGIC_VECTOR (N downto 1); 
      Vss : in STD_LOGIC_VECTOR (N downto 1); 
      Vdd : in STD_LOGIC_VECTOR (N downto 1); 
      DA : out STD_LOGIC_VECTOR (N downto 1)); 
end Registre; 

architecture Behavioral of Registre is 

    component SA_REG 
     Port (EC : in STD_LOGIC; 
       C : in STD_LOGIC; 
       R : in STD_LOGIC; 
       S : in STD_LOGIC; 
       Q : out STD_LOGIC; 
       Vss : in STD_LOGIC; 
       Vdd : in STD_LOGIC); 
    end component; 

    Component SA_REGDR 
     Port (R : in STD_LOGIC; 
       C : in STD_LOGIC; 
       EC : in STD_LOGIC; 
       Q : out STD_LOGIC; 
       Vss: in STD_LOGIC; 
       Vdd: in STD_LOGIC 
      ); 
    end component; 

begin 

    DR : SA_REGDR port map (R=> R(10) ,EC=> EC(10), C=> C(10), Vss=> Vss(10), Vdd=> Vdd(10), Q=> DA(10)); 

    Mgen : for i in 1 to N-1 generate 
     M : SA_REG port map (R=>R(i), EC=> EC(i), C=> C(i),S=> S(i), Vss=> Vss(i), Vdd=> Vdd(i), Q=> DA(i)); 
    end generate; 

end Behavioral;

試驗檯：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.std_logic_unsigned.all; 
use IEEE.numeric_std.all; 

entity Registre_tb is 
end Registre_tb; 

architecture Behavioral of Registre_tb is 
    component Registre 
     generic(N : integer :=10); 
     Port (R : in STD_LOGIC_VECTOR (10 downto 1); 
       EC : in STD_LOGIC_VECTOR (10 downto 1); 
       C : in STD_LOGIC_VECTOR (10 downto 1); 
       S : in STD_LOGIC_VECTOR (10 downto 1); 
       Vss : in STD_LOGIC_VECTOR (10 downto 1); 
       Vdd : in STD_LOGIC_VECTOR (10 downto 1); 
       DA : out STD_LOGIC_VECTOR (10 downto 1)); 
    end component; 

    signal Ri : STD_LOGIC_VECTOR (10 downto 1):= (others => '0'); 
    signal Ci : STD_LOGIC_VECTOR (10 downto 1):= (others => '0'); 
    signal ECi : STD_LOGIC_VECTOR (10 downto 1):= (others => '0'); 
    signal Si : STD_LOGIC_VECTOR (10 downto 1):= (others => '0'); 
    signal Vssi: STD_LOGIC_VECTOR (10 downto 1):= (others => '0'); 
    signal Vddi: STD_LOGIC_VECTOR (10 downto 1):= (others => '1'); 
    signal DAi : STD_LOGIC_VECTOR (10 downto 1); 

    signal clk : std_logic := '0'; 
begin 
    -- instanciate 
    component_in_test : Registre port map(--instantiation of the Registre component 
     R => Ri, 
     C => Ci, 
     EC => ECi, 
     S => Si, 
     Vss => Vssi, 
     Vdd => Vddi, 
     DA => DAi 
    ); 

    -- stimulis 
    clk <= not clk after 1ns; --creates 100MHz clock inside testbench 

    Ri_gen : process(clk) is --process which will check Ri with every possible value 
    begin 
     if clk'Event and clk = '1' then 
      Ri <= Ri + 1; 
     end if; 
    end process; 

    Ci_gen : process(clk) is --process which will check Ci with every possible value 
    begin 
     if clk'Event and clk = '1' then 
      Ci <= Ci + 1; 
     end if; 
    end process; 

    ECi_gen : process(clk) is --process which will check ECi with every possible value 
    begin 
     if clk'Event and clk = '1' then 
      ECi <= ECi + 1; 
     end if; 
    end process; 

    Si_gen : process(clk) is --process which will check Si with every possible value 
    begin 
     if clk'Event and clk = '1' then 
      Si <= Si + 1; 
     end if; 
    end process; 

end Behavioral;

模擬 enter image description here

來源

2014-06-07 user3212448

見最長靜態前綴的討論在VHDL FAQ：http://www.eda.org/comp.lang.vhdl/FAQ1.html#drivers

出於這個原因，你需要重新寫你的實例爲：

Mgen : for i in 1 to N generate 
    If_N : if i = N generate 
    DR : SA_REGDR port map (R=> R(10) ,EC=> EC(10), C=> C(10), Vss=> Vss(10), Vdd=> Vdd(10), Q=> DA(10)); 
    end generate ; 

    if_OTHERS : if i /= N generate 
    M : SA_REG port map (R=>R(i), EC=> EC(i), C=> C(i),S=> S(i), Vss=> Vss(i), Vdd=> Vdd(i), Q=> DA(i)); 
    end generate ; 
end generate;

來源

2014-06-07 15:32:04

非常感謝，通過修改實例並修復信號'Si to 1'信號Si：STD_LOGIC_VECTOR（10 downto 1）：=（others =>'1' ）;」，但錯誤總是出現在輸出10「DA（10）它固定在」Z「 – user3212448

我不明白。除了第10位之外的所有內容都被映射到SA_REG並保持不變。什麼改變了？如預期的那樣，位1已切換'z'=>'0'。什麼改變了？ – Val

不，位10映射到組件SA_REGDR被切換到'Z'，而不是位1 – user3212448

調試=降低的問題最小。關於VHDL，您可以將所有東西都實例化爲實體，例如

U1: entity MY_IMPLEMENTATION port map()

爲了消除需要在任何地方聲明組件。您可以公開它們的實現，而不是聲明SA_REG和SA_REGDR組件。

您的SA_REGDR卡在位10，而N用於SA_REG實例化是可變的。你正在準備不一致的理由。

輸出DA（i）由SA_REG和SA_REGDR確定，其實現保密。因此，我們當然無法回答這個問題。然而，'z'值意味着其中一個輸入是driver enable。當您遞增輸入時，輸入的較低有效位將切換爲0 - > 1，並且其驅動器被啓用，以便最低有效輸出位切換高阻抗=>具體值。沒有足夠的信息來解釋爲什麼你在LSB中得到0而不是1或其他任何東西。

Actually, other signals can stay unresolved。只有DA（i）必須是std_logic。

來源

2014-06-07 13:53:14 Val

感謝您的澄清，我會把實現od sa_REG和Sa_rREGDR – user3212448

VHDL Testbench代碼不適用於寄存器

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