VHDL變化CLK速度

Question

從這個代碼創建的塊，然後添加CLK，KEY [0]和LEDR [0:15]

library ieee; 
use ieee.std_logic_1164.all; 

--library work; 
--use work.car_pkg.all; 


entity knight_rider2 is 
    port ( clk, resetn, clock_button : in std_logic; 
     led1, led2, led3, led4, led5, led6, led7, led8, 
     led9, led10, led11, led12, led13, led14, led15 : out std_logic); 
end entity knight_rider2; 



architecture fsm of knight_rider2 is 
    type state_types is (start, forward1, forward2, forward3, 
    forward4, forward5, forward6, forward7, forward8, forward9, 
    forward10,forward11,forward12, forward13, forward14); 


    signal state: state_types; 
    signal led_states : std_logic_vector(14 downto 0); 

begin 

      count : process(clk, resetn, clock_button) 
begin 
    if clock_button = '0' then 
    counter <= 0; 
    fsm_pulse <= '0'; 
    else 
    if rising_edge(clk) then 
     counter  <= counter + 1; 
     fsm_pulse <= '0'; 
     if counter = divider then 
     fsm_pulse <= '1'; 
     counter <= 0; 
     end if; 
    end if; 
    end if; 
end process; 


    combined_next_current: process (clk, resetn, clock_button) 
    begin 
     if (resetn = '0') then 
      state <= start; 
     elsif rising_edge(clk) then 
      if fsm_pulse = '1' then 
      case state is 

       when start => 
        state <= forward1; 

       when forward1 =>     
        state <= forward2;    


       when forward2 =>      
         state <= forward3;    

       when forward3 =>    
         state <= forward4;    

       when forward4 =>      
         state <= forward5;     


       when forward5 =>     
         state <= forward6;     


       when forward6 =>      
         state <= forward7;     


       when forward7 =>     
          state <= forward8;    

       when forward8 =>      
          state <= forward9;  


       when forward9 =>      
          state <= forward10;      

       when forward10 =>      
          state <= forward11; 


       when forward11 =>     
          state <= forward12;     


       when forward12 =>      
          state <= forward13; 


       when forward13 =>      
          state <= forward14; 



       when forward14 => state <=start; 

       when others => 
       state <= forward1; 

      end case; 
     end if; 
    end process; 


    --combinational output logic 

    --internal signal to control state machine transistions 


    led_select : process(state) 
begin 
    case state is 
    when forward1 => 
    led_states <= "000000000000011"; 
    when forward2 => 
    led_states <= "000000000000110"; 
    when forward3 => 
    led_states <= "000000000001100"; 
    when forward4 => 
    led_states <= "000000000011000"; 
    when forward5 => 
    led_states <= "000000000110000"; 
    when forward6 => 
    led_states <= "000000001100000"; 
    when forward7 => 
    led_states <= "000000011000000"; 
    when forward8 => 
    led_states <= "000000110000000"; 
    when forward9 => 
    led_states <= "000001100000000"; 
    when forward10 => 
    led_states <= "000011000000000"; 
    when forward11=> 
    led_states <= "000110000000000"; 
    when forward12=> 
    led_states <= "001100000000000"; 
    when forward13=> 
    led_states <= "011000000000000"; 
    when forward14=> 
    led_states <= "110000000000000"; 
    when others => 
    led_states <= "100000000000001"; 

    end case; 
end process; 

led1 <= led_states(0); 
led2 <= led_states(1); 
led3 <= led_states(2); 
led4 <= led_states(3); 
led5 <= led_states(4); 

led6 <= led_states(5); 
led7 <= led_states(6); 
led8 <= led_states(7); 
led9 <= led_states(8); 
led10 <= led_states(9); 

led11 <= led_states(10); 
led12 <= led_states(11); 
led13 <= led_states(12); 
led14 <= led_states(13); 
led15 <= led_states(14); 





end; 

但現在我想添加KEY [1]按鈕來改變速度，例如：

第一壓：2 * F

2壓：4 * F

3按：8 * F

4按：F

按5：2 * F等

所以，我怎樣才能改變這種代碼做我想要什麼？

Answer 1

你可以改變你的狀態機在通過使用計數器運行，例如速度：

-- Generate a counter at your main clock frequency 
-- counter is declared as an integer. 
count : process(clock, resetn) 
begin 
    if resetn = '0' then 
    counter <= 0; 
    fsm_pulse <= '0'; 
    else 
    if rising_edge(clock) then 
     counter  <= counter + 1; 
     fsm_pulse <= '0'; 
     if counter = divider then 
     fsm_pulse <= '1'; 
     counter <= 0; 
     end if; 
    end if; 
    end if; 
end process; 

新的信號，聲明如下：

signal fsm_pulse : std_logic; 
signal counter : integer; 
signal divider : integer; 

然後，在你的FSM進程可以使用您生成的fsm_pulse觸發狀態轉換：

combined_next_current: process (clk, resetn) 
begin 
    if (resetn = '0') then 
     state <= start; 
    elsif rising_edge(clk) then 
     if fsm_pulse = '1' then 
     case state is 
      when start => 
       state <= forward1; 
      when forward1 =>     
       state <= forward2; 

     ... 

     etc (your remaining states) 
     end if; 

只要計數器達到您選擇的分頻器值，fsm_pulse就會在單個時鐘週期內設置爲'1'。分頻器值代表您希望每個FSM轉換髮生之後所需要的時鐘週期數，例如零分頻器將使FSM在主時鐘頻率轉換，而1分頻器將使FSM轉換爲主時鐘頻率的一半。