計數器系統verilog代碼

Question

我有這個計數器的問題。輸出全是xxxxxxxx，我知道我應該將count的初始值和溢出設置爲0，但它會給出錯誤。這是代碼：

// Code your design here 
module counter (in, start, count, clk, overflow); 

input [3:0] in; 
input clk; 
input start; 
output reg [7:0] count; 
output reg overflow; 
//reg count; 
//count =0; 
//overflow=0; 
always @ (posedge clk) 
    begin 
    if (start) begin 
     count <= 8'b0; 
     overflow <= 1'b0; 
    end 

    else if (in == 4'b0101) begin 
     count <= count+1; 
    end 
    if (count == 4'b1111) begin 
     overflow <=1'b1; 
    end 
    end 

endmodule 

這是測試平臺：

// Code your testbench here 
// or browse Examples 
module tb(); 

    reg [3:0] in; 
    reg clk,start; 
    wire [7:0] count; 
    reg overflow = 1'b0; 

    initial begin 

    $display ("time\t clk start in count overflow"); 
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow); 

    clk=0; 
    in=0; 
    start=0; 
    // overflow=0; 
    // count=0; 

    #5 in=4'd1; 
    #5 in=4'd5; 
    #5 in=4'd4; 
    #5 in=5'd5; 
    #5 in=4'd1; 
    #5 in=4'd5; 
    #5 in=4'd4; 
    #5 in=5'd5; 
    #5 in=4'd1; 
    #5 in=4'd5; 
    #5 in=4'd4; 
    #5 in=5'd5; 
    #5 in=4'd1; 
    #5 in=4'd5; 
    #5 in=4'd4; 
    #5 in=5'd5; 
    #50 $finish; 

    end 

    always #5 clk=~clk; 

    counter u0(.*); 

endmodule 

我知道這是一個簡單的問題，但我很感激，如果你們幫幫忙。

Answer 1

有兩個問題需要解決。

1）巧合地in = 5僅在時鐘的負邊沿期間設置。這是因爲clk週期是＃10，並且tb代碼每＃5改變「in」值。當計數器檢查posedge中的in值時，它忽略in = 5。時間段需要＃10或TB在設置信號「in」之前可以等待clk的時間。 2）需要爲計數器設置開始重置，否則計數= x（未知）和計數+ 1 => x + 1的值等於x。因此，櫃檯不會增加，並始終保持x。

更新後的tb如下。

module tb(); 

    reg [3:0] in; 
    reg clk,start; 
    wire [7:0] count; 
    reg overflow = 1'b0; 

    initial begin 

    $display ("time\t clk start in count overflow"); 
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow); 

    clk=0; 
    in=0; 
    start=0; 
    // overflow=0; 
    // count=0; 

    #10 start = 1'b1; // reset counter 
    #10 start = 1'b0; 
    #10 in=4'd1; 
    #10 in=4'd5; 
    #10 in=4'd4; 
    #10 in=5'd5; 
    #10 in=4'd1; 
    #10 in=4'd5; 
    #10 in=4'd4; 
    #10 in=5'd5; 
    #10 in=4'd1; 
    #10 in=4'd5; 
    #10 in=4'd4; 
    #10 in=5'd5; 
    #10 in=4'd1; 
    #10 in=4'd5; 
    #10 in=4'd4; 
    #10 in=5'd5; 
    #50 $finish; 

    end 

    always #5 clk=~clk; 

    counter u0(.*); 

initial // Dump waveform for debug 
$dumpvars; 

endmodule 

您可以使用$ dumpvars命令轉儲波形以進行調試。

替代代碼（使用posedge事件驅動的測試臺數據）

// Code your testbench here 
// or browse Examples 
module tb(); 

    reg [3:0] in; 
    reg clk,start; 
    wire [7:0] count; 
    reg overflow = 1'b0; 

    initial begin 

    $display ("time\t clk start in count overflow"); 
    $monitor ("%g\t %b %b %b %b", $time, clk, start, in, count, overflow); 

    clk=0; 
    in=0; 
    start=0; 
    // overflow=0; 
    // count=0; 

    @(posedge clk) start = 1'b1;// reset counter 
    @(posedge clk) start = 1'b0; 
    @(posedge clk) in=4'd1; 
    @(posedge clk) in=4'd5; 
    @(posedge clk) in=4'd4; 
    @(posedge clk) in=5'd5; 
    @(posedge clk) in=4'd1; 
    @(posedge clk) in=4'd5; 
    @(posedge clk) in=4'd4; 
    @(posedge clk) in=5'd5; 
    @(posedge clk) in=4'd1; 
    @(posedge clk) in=4'd5; 
    @(posedge clk) in=4'd4; 
    @(posedge clk) in=5'd5; 
    @(posedge clk) in=4'd1; 
    @(posedge clk) in=4'd5; 
    @(posedge clk) in=4'd4; 
    @(posedge clk) in=5'd5; 
    #50 $finish; 

    end 

    always #5 clk=~clk; 

    counter u0(.*); 

initial 
$dumpvars; 

endmodule