測試臺和代碼驗證（VHDL）

Question

我是VHDL的新手。我寫了一個遞減計數器的代碼，其中計數器從數組中取出整數並將其計數到零並遞增檢查輸出。我希望你們能夠驗證代碼在邏輯上是否正確。 如果是的話，我該如何使用測試臺進行測試。

entity counter is 
    port(clk : in bit; 
     check : out integer); 
end counter;  

architecture imp of counter is 
    type my_array is array(natural range<>) of integer; 
    constant set:my_array(1 to 5):= (2,4,6,8,10);--array of 5 integers 
    signal count:integer:=set(1); --initiating count with integer at first location of array 
    signal t : integer; 
begin 
    process(clk) 
     variable i : integer:= 1;--to be used to indicate the locations of array 
    begin 
     if (clk='1' and clk'event) and (count>0) then 
     count<=count-1; 
     elsif (clk='1' and clk'event) and (i<5) then 
     i:=i+1; 
     count<= set(i); 
     t<=t+1; 
     end if; 
    end process; 
    check<=t; 
end imp; 

Answer 1

該代碼很好，但您需要設置初始值爲t進行仿真。要了解如何使用VHDL編寫測試平臺，請參閱Test Benches Overview。

下面是一個簡單的：

entity counter_tb is 
end; 

architecture arch of counter_tb is 

    component counter is 
     port (clk : in bit; 
      check : out integer); 
    end component; 

    signal clk: bit; 
    signal check: integer; 
begin 

    UUT: counter 
     port map (clk => clk, check => check); 

    clk_proc: process 
    begin 
     clk <= '0'; 
     wait for 50 ns; 
     clk <= '1'; 
     wait for 50 ns; 
    end process; 

end arch; 

Answer 2

您的代碼編譯正確，但我們需要的是應該做的事情，以確保它是正確的更詳細的說明。正如@tsukuyo所說，你還需要在＃10行中給一個初始值指示't'。

修復了這個問題之後，下面是一個測試臺，它可以鍛鍊你的電路並自動檢查輸出值。檢查測試平臺中的輸出值非常重要，因爲這樣您每次更改代碼時都不必盯着波形。由於測試平臺是自檢，它會自動告訴你什麼是錯的：

use std.textio.all;              
use std.env.all;               

entity counter_tb is              
end;                  

architecture testbench of counter_tb is         
    signal clk: bit;              
    signal check: integer;             

begin                  
    -- instantiate the unit under test          
    uut: entity work.counter port map(clk => clk, check => check); 

    -- generate a clock pulse with a 20 ns period       
    clk <= not clk after 10 ns;           

    run_tests: process is             
     -- declare an array with all expected output values     
     type integer_vector is array(natural range<>) of integer;   
     constant EXPECTED_RESULTS: integer_vector := (      
     0, 0, 0,               
     1, 1, 1, 1, 1,             
     2, 2, 2, 2, 2, 2, 2,            
     3, 3, 3, 3, 3, 3, 3, 3, 3,          
     4, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4         
    );                 
     variable log_line: line;           

    begin                 
     -- loop through all expected values and ensure that     
     -- they match the actual output value        
     for i in EXPECTED_RESULTS'range loop        
     wait until rising_edge(clk);          
     write(log_line,             
      "i: " & to_string(i) &          
      ", check: " & to_string(check) &        
      ", expected: " & to_string(EXPECTED_RESULTS(i))    
     );                
     writeline(output, log_line);          
     assert check = EXPECTED_RESULTS(i);        
     end loop;               

     report "End of simulation. All tests passed.";      
     finish;                
    end process;               

end;  

這是它產生的輸出的一個例子：

# Loading std.standard 
# Loading std.textio(body) 
# Loading std.env(body) 
# Loading work.counter_tb(testbench) 
# Loading work.counter(imp) 
# run -all 
# i: 0, check: 0, expected: 0 
# i: 1, check: 0, expected: 0 
# i: 2, check: 0, expected: 0 
# i: 3, check: 1, expected: 1 
# i: 4, check: 1, expected: 1 
# i: 5, check: 1, expected: 1 
# i: 6, check: 1, expected: 1 
# i: 7, check: 1, expected: 1 
# i: 8, check: 2, expected: 2 
# i: 9, check: 2, expected: 2 
# i: 10, check: 2, expected: 2 
# i: 11, check: 2, expected: 2 
# i: 12, check: 2, expected: 2 
# i: 13, check: 2, expected: 2 
# i: 14, check: 2, expected: 2 
# i: 15, check: 3, expected: 3 
# i: 16, check: 3, expected: 3 
# i: 17, check: 3, expected: 3 
# i: 18, check: 3, expected: 3 
# i: 19, check: 3, expected: 3 
# i: 20, check: 3, expected: 3 
# i: 21, check: 3, expected: 3 
# i: 22, check: 3, expected: 3 
# i: 23, check: 3, expected: 3 
# i: 24, check: 4, expected: 4 
# i: 25, check: 4, expected: 4 
# i: 26, check: 4, expected: 4 
# i: 27, check: 4, expected: 4 
# i: 28, check: 4, expected: 4 
# i: 29, check: 4, expected: 4 
# i: 30, check: 4, expected: 4 
# i: 31, check: 4, expected: 4 
# i: 32, check: 4, expected: 4 
# i: 33, check: 4, expected: 4 
# i: 34, check: 4, expected: 4 
# ** Note: End of simulation. All tests passed. 
# Time: 690 ns Iteration: 0 Instance: /counter_tb                

注意：在使用的ModelSim運行上述模擬，輸入：

vlib work 
vcom -2008 *.vhd 
vsim -c counter_tb(testbench) -do "run -all; quit"