SR Fliflop的VHDL測試平臺

Question

我想用VHDL實現SR觸發器。我編寫了觸發器的代碼以及測試平臺。但測試平臺不能正確編譯，並給出我無法弄清楚的錯誤。我正在使用ghdl進行編譯。請幫忙。

這是觸發器的代碼。

library ieee; 
use ieee.std_logic_1164.all; 

entity sr_flipflop is 
    port 
    (
     s,r,clock: in std_logic; 
     q,qbar: inout std_logic 
    ); 
end sr_flipflop; 

architecture arc of sr_flipflop is 
    signal x,y: std_logic; 
begin 
    process (clock,s,r) begin 
     x<=r and clock; 
     y<=s and clock; 
     q<=qbar nor x after 10 ns; 
     qbar<=q nor y after 10 ns; 
    end process; 
    process (x,y) begin 
     q<=qbar nor x after 5 ns; 
     qbar<=q nor y after 5 ns; 
    end process; 
end architecture arc; 

這是測試平臺的代碼。

library ieee; 
use ieee.std_logic_1164.all; 

entity sr_flipflop_tb is 
end entity sr_flipflop_tb; 

architecture arc of sr_flipflop is 
    component sr_flipflop is 
     port 
     (
      s,r,clock: in std_logic; 
      q,qbar: inout std_logic 
     ); 
    end component sr_flipflop; 

    signal clock:std_logic:='0'; 
    signal s,r:std_logic; 
    signal q:std_logic:='0'; 
    signal qbar:std_logic:='1'; 
    constant half_period:time:=30 ns; 

begin 
    port_map:sr_flipflop port map(clock=>clock,s=>s,r=>r,q=>q,qbar=>qbar); 

    process begin 
     clock <= not clock after half_period; 
    end process; 
    process begin 
     s<='0'; 
     r<='0'; 

     s<='0' after 40 ns; 
     r<='1' after 40 ns; 

     s<='1' after 80 ns; 
     r<='0' after 80 ns; 

     s<='1' after 120 ns; 
     r<='1' after 120 ns; 
    end process; 

end architecture arc; 

的第一個文件編譯沒有錯誤，但是當我給在CMD下面的命令，

ghdl -a sr_flipflop_tb.vhd 

我收到以下錯誤：

sr_flipflop_tb.vhd:16:15: identifier 'clock' already used for a declaration 
sr_flipflop.vhd:7:20: previous declaration: port "clock" 
sr_flipflop_tb.vhd:17:15: identifier 's' already used for a declaration 
sr_flipflop.vhd:7:16: previous declaration: port "s" 
sr_flipflop_tb.vhd:17:17: identifier 'r' already used for a declaration 
sr_flipflop.vhd:7:18: previous declaration: port "r" 
sr_flipflop_tb.vhd:18:15: identifier 'q' already used for a declaration 
sr_flipflop.vhd:8:16: previous declaration: port "q" 
sr_flipflop_tb.vhd:19:15: identifier 'qbar' already used for a declaration 
sr_flipflop.vhd:8:18: previous declaration: port "qbar" 
sr_flipflop_tb.vhd:26:16: port "clock" can't be assigned 
sr_flipflop_tb.vhd:29:16: port "s" can't be assigned 
sr_flipflop_tb.vhd:30:16: port "r" can't be assigned 
sr_flipflop_tb.vhd:32:16: port "s" can't be assigned 
sr_flipflop_tb.vhd:33:16: port "r" can't be assigned 
sr_flipflop_tb.vhd:35:16: port "s" can't be assigned 
sr_flipflop_tb.vhd:36:16: port "r" can't be assigned 
sr_flipflop_tb.vhd:38:16: port "s" can't be assigned 
sr_flipflop_tb.vhd:39:16: port "r" can't be assigned 

請一些啓發。謝謝。在您的測試平臺

Answer 1

7號線是

architecture arc of sr_flipflop is 

這似乎是一個複製粘貼&錯誤，應該是

architecture arc of sr_flipflop_tb is 

這應當引起這些錯誤消息。

請注意，您的代碼本身並不完美。在Modelsim中，你的測試平臺根本不能運行（我不知道GHDL）。也許退房this tutorial。它有點過時了，但它工作。

Answer 2

這

entity sr_flipflop_tb is 
end entity sr_flipflop_tb; 

architecture arc of sr_flipflop is 

應該是這個

entity sr_flipflop_tb is 
end entity sr_flipflop_tb; 

architecture arc of sr_flipflop_tb is 
        ^^^^^^^^^^^^^^ 

Answer 3

不回答你的問題，但是

process (clock,s,r) begin 
    x<=r and clock; 
    y<=s and clock; 
    q<=qbar nor x after 10 ns; 
    qbar<=q nor y after 10 ns; 
end process; 
process (x,y) begin 
    q<=qbar nor x after 5 ns; 
    qbar<=q nor y after 5 ns; 
end process; 

你有兩個進程駕駛q和q_bar。這不會按預期工作。由於多個驅動程序，信號將解析爲'X'。

---

下一個問題是敏感列表。

process (x,y) begin 
    q<=qbar nor x after 5 ns; 
    qbar<=q nor y after 5 ns; 
end process; 

q和q_bar不在靈敏度列表上。因此，q和q_bar將不會更新，如果任一q_bar， q已更新。

---

下一個問題是信號更新。

信號將不會更新，直到下一個增量週期。過程完成後會發生增量循環。所以：

process (clock,s,r) begin 
    x<=r and clock; 
    q<=qbar nor x after 10 ns; 
end process; 

在x由於r或clock變化的變化將不會在此下一行適用於q，因爲x不會直到下一個增量週期進行更新。

---

最後，不要使用inout端口類型。

如果您想內部訪問輸出端口，可以使用VHDL-2008進行編譯，也可以使用中間信號。

architecture ... of ... 
    signal q_int : std_logic; 
begin 
    [... assign and use q_int] 
    q <= q_int; 
end architecture; 

但最好開始使用VHDL-2008