系統Verilog測試產生2個時鐘相同的頻率有90度的相位

Question

對於系統Verilog測試我需要創建2個時鐘與參數

時鐘1 = 250MHz的，開始相位0degrees

時鐘2 = 250MHz的，開始階段90degrees wrt時鐘1

我試過以下，但它對時鐘生成沒有影響，並且兩者仍然處於同相。我該如何實現這一階段轉變？

parameter CLK_PERIOD = 4000; //250MHz = 4000ps 

    initial 
    Clock1 = 1'b0; 
    always 
    Clock1= #(CLK_PERIOD/2.0) ~Clock1; 

    initial begin 
    Clock2 = 1'b0; 
    #1000; //to make it 90degrees out of phase with Clock1 
    end 
    always 
    Clock2= #(CLK_PERIOD/2.0) ~Clock2; 

Answer 1

使用forever的Clock2initial塊內：

module tb; 
    parameter CLK_PERIOD = 4000; //250MHz = 4000ps 
    bit Clock1, Clock2; 
    initial 
    Clock1 = 1'b0; 
    always 
    Clock1= #(CLK_PERIOD/2.0) ~Clock1; 

    initial begin 
    Clock2 = 1'b0; 
    #1000; //to make it 90degrees out of phase with Clock1 
    forever Clock2= #(CLK_PERIOD/2.0) ~Clock2; 
    end 
endmodule