將這些模塊從verilog轉換爲VHDL

Question

請任何人都可以幫助我將以下Verilog轉換爲vhdl。謝謝。

module adder(a,b,out); //adder 

input [31:0] a,b; //inputs 
output [31:0] out; //outputs 
reg [31:0] out; 
always @(a or b) begin 
    out = a+b; 
end 
endmodule 

Answer 1

LIBRARY ieee; 
USE ieee.std_logic_1164.all; 
use ieee.numeric_std.all; 

entity adder is 
    PORT ( 
    a : in std_logic_vector(31 downto 0); 
    b : in std_logic_vector(31 downto 0); 
    regout : out std_logic_vector (31 downto 0) 
); 
end adder; 

ARCHITECTURE adder_arch of adder is 
begin 

regout <= std_logic_vector(unsigned(a) + unsigned(b)); 

end adder_arch;