VHDL：賽靈思碼錯誤

我們得到這個錯誤集：VHDL：賽靈思碼錯誤

Line 23: Mismatch in number of elements assigned in conditional signal assignment 
Line 23: Expression has 1 elements ; expected 7

有了這個代碼，第23行是

Q_out <= "1111110" when Q_in = "0000" else 


library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.NUMERIC_STD.ALL; 

-- Uncomment the following library declaration if instantiating 
-- any Xilinx primitives in this code. 
--library UNISIM; 
--use UNISIM.VComponents.all; 

entity decoder is 
Port (
     Q_in : in UNSIGNED (3 downto 0); 
     Q_out : out UNSIGNED (6 downto 0) 
); 
end decoder; 
architecture behavioral  of decoder is 
begin 
Q_out <= "1111110" when Q_in = "0000" else 
     "0110000" when Q_in = "0001" else 
     "1101101" when Q_in = "0010" else 
     "1111001" when Q_in = "0011" else 
     "0110011" when Q_in = "0100" else 
     "1011011" when Q_in = "0101" else 
     "0011111" when Q_in = "0110" else 
     "1110000" when Q_in = "0111" else 
     "1111111" when Q_in = "1000" else 
     "1110011" when Q_in = "1001" else 
     "X"; 


end behavioral ;

來源

2014-01-25 user3235290

嘗試「XXXXXXX」; ... –

布賴恩：它的工作！非常感謝！我發現這個奇怪的因爲同學們剛剛使用過「X」，即使是沒有簽名的數組，演講也只是使用「X」的例子。無論如何，從錯誤中應該已經發現，過於集中於一行！ Ta！ – user3235290

您也可以使用'（others =>'X'）'使它填充任意長度的'X'，這樣更容易維護和重用。 –

VHDL是強類型的，這意味着當你分配的信號，你需要匹配端口寬度和類型。在你的情況下，你沒有匹配端口寬度，這是錯誤告訴你的。您正試圖將1位寬的內容分配給7位寬的內容。嘗試：

"1110011" when Q_in = "1001" else 
(others => 'X');

在VHDL的others關鍵字意味着它將填補多少X需要的適當匹配端口寬度。

來源

2014-01-25 21:09:33 Russell

VHDL：賽靈思碼錯誤

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