我試圖在VHDL語言ROM,我使用這個模板我在http://www.edaboard.com/thread38052.html發現:的Python:代碼VHDL代碼生成
library ieee;
use ieee.std_logic_1164.all;
entity ROM is
port (address : in std_logic_vector(3 downto 0);
data : out std_logic_vector(7 downto 0));
end entity ROM;
architecture behavioral of ROM is
type mem is array (0 to 2**4 - 1) of std_logic_vector(7 downto 0);
constant my_Rom : mem := (
0 => "00000000",
1 => "00000001",
2 => "00000010",
3 => "00000011",
4 => "00000100",
5 => "11110000",
6 => "11110000",
7 => "11110000",
8 => "11110000",
9 => "11110000",
10 => "11110000",
11 => "11110000",
12 => "11110000",
13 => "11110000",
14 => "11110000",
15 => "11110000");
begin
process (address)
begin
case address is
when "0000" => data <= my_rom(0);
when "0001" => data <= my_rom(1);
when "0010" => data <= my_rom(2);
when "0011" => data <= my_rom(3);
when "0100" => data <= my_rom(4);
when "0101" => data <= my_rom(5);
when "0110" => data <= my_rom(6);
when "0111" => data <= my_rom(7);
when "1000" => data <= my_rom(8);
when "1001" => data <= my_rom(9);
when "1010" => data <= my_rom(10);
when "1011" => data <= my_rom(11);
when "1100" => data <= my_rom(12);
when "1101" => data <= my_rom(13);
when "1110" => data <= my_rom(14);
when "1111" => data <= my_rom(15);
when others => data <= "00000000";
end case;
end process;
end architecture behavioral;
好了,問題是,我希望把我的ROM 2000值。所以我想知道如何讓未來使用python:
想象一下,你在一個.txt文件必須在接下來的格式這樣的數據:
0 45
1 56
2 78
3 98
因此,該程序將與數據做到這一點:
0 => "00101101"
1 => "00111000"
2 => "01001110"
3 => "01100010"
那麼這些值 「00101101」, 「00111000」, 「01001110」, 「01100010」 是45,56,78 y的二進制表示89. 所以,你的想法的respectives值...
有一個小細節,需要指定用於表示的位數:如果你難道你不能夠得到這個 :
0 => "101101"
1 => "111000"
2 => "1001110"
3 => "1100010"
謝謝你這麼多的代碼做一切可能的碎片這一計劃
+1不想做的事情很長的路要走! – Marty 2011-02-11 12:42:49
2000值太多了!!! :) – Peterstone 2011-02-11 16:18:34