爲什麼賽靈思ISE不會在狀態機中接受此聲明？

Question

所以我目前正在做一個涉及hd44780顯示器的小項目。但是因爲我想寫我自己的init序列，我決定使用一個狀態機。對於FPGA來說，我對他們的編程來自Java背景頗爲陌生。

這是我的狀態機塊。

我這個狀態它的工作和IDE不顯示任何錯誤。

always @(posedge reset) 
    begin 
    en_timeout <= 2'b00; 
    timeout <= 14'b00000000000000; 
    init <= 4'b000; 
    data <= 8'b00000000; 
    en <= 1'b1; //active low 
    rs <= 1'b0; 
    rw <= 1'b0; 
    state <= 4'b0000; 
    next_state <= 4'b0000; 

    debug <= 1'b0; 
    end 

if(timeout == 0) 
    begin //Begin of Initiation state machine 
     case(state) 
      s0: 
       begin 
       end 

      s1: 
       begin 
       end 
      s2: 
       begin 
       end 
      s3: 
       begin 
       end 
      s4: 
       begin 
       end 
      s5: 
       begin 
       end 
      s6: 
       begin 
       end 
      s7: 
       begin 
       end 
      s8: 
       begin 
       end 
      s9: 
       begin 
       end 
      s10: 
       begin 
       end 
      normal: 
       begin 
       end 
     endcase 
    end //End of Initiation state machine 

但是，如果我添加了開始和狀態的一個末端之間的任何分配它爲我「行n：附近有語法錯誤」 < =「」

例如：

  case(state) 
      s0: 
       begin 
       state <= s1; 
       end 

我DisplayDriver的全部代碼至今：

module DisplayDriver(
    output reg [8:0] data, 
    output reg en, 
    output reg rs, 
    output reg rw, 
    output reg debug, 
    input clk, 
    input reset 
    ); 

    parameter s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,s9=9,s10=10,normal = 11; 

    reg [3:0] state; // 4 bit for max 11 combinations s0-s10 and normal 
    reg [3:0] state; // 4 bit for max 11 combinations s0-s10 and normal [next State] 
    reg [1:0] en_timeout; // 2 bit for en high to low to high cylce 
    reg [13:0] timeout; // 14 bit 

    initial 
    // begin init 
     begin 
     en_timeout <= 2'b00; 
     timeout <= 14'b00000000000000; 
     init <= 4'b000; 
     data <= 8'b00000000; 
     en <= 1'b1; //active low 
     rs <= 1'b0; 
     rw <= 1'b0; 
     state <= 4'b0000; 
     next_state <= 4'b0000; 

     debug <= 1'b0; 
     end 
    // end of init 

    always @(posedge clk) 
    //begin of everything that needs the clock 
    begin 
     if(en_timeout > 0) //begin timeout stack 
      begin 
      en_timeout <= en_timeout -1; 
      en <= ~en;// if en_timeout = 2 -> en = 0; if en_timeout = 1 -> en = 1; 
      end 
     else if (timeout > 0) timeout <= timeout -1; //end timeout stack 

     if(timeout == 0)state <= next_state; 
    end //end of everything that needs the clock 


    always @(posedge reset) 
     begin 
     en_timeout <= 2'b00; 
     timeout <= 14'b00000000000000; 
     init <= 4'b000; 
     data <= 8'b00000000; 
     en <= 1'b1; //active low 
     rs <= 1'b0; 
     rw <= 1'b0; 
     state <= 4'b0000; 
     next_state <= 4'b0000; 

     debug <= 1'b0; 
     end 

    if(timeout == 0) 
     begin //Begin of Initiation state machine 
      case(state) 
       s0: 
        begin 
        end 

       s1: 
        begin 
        end 
       s2: 
        begin 
        end 
       s3: 
        begin 
        end 
       s4: 
        begin 
        end 
       s5: 
        begin 
        end 
       s6: 
        begin 
        end 
       s7: 
        begin 
        end 
       s8: 
        begin 
        end 
       s9: 
        begin 
        end 
       s10: 
        begin 
        end 
       normal: 
        begin 
        end 
      endcase 
     end //End of Initiation state machine 
endmodule 

有沒有人有一個想法，爲什麼它的行爲這樣？

Answer 1

我假設你正試圖爲「狀態」合成一個寄存器，在這種情況下，更新「< =」需要始終在（@posedge clk）內。