試圖在vhdl中實現spi總線

Question

我一直試圖通過SPI與LTC2426 DAC通信，並且我失敗了。現在我正在尋求幫助。有人可以告訴我爲什麼我的代碼不起作用。 CSDAC正常工作，生成SCLK併發送32位，但我仍然可能已經搞亂了時序。我會非常感謝有人幫我修復代碼。

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity DAC is 
    port 
     (
      CLK : in STD_LOGIC;   
      SCLK : out STD_LOGIC; 
      MOSI : out STD_LOGIC; 
      CSDAC : out STD_LOGIC := '1'   
     ); 
end DAC; 

architecture Behavioral of DAC is 
Signal Counter : Integer range 0 to 32 := 0; 
Signal CurrentBit : Integer range 0 to 32 := 0; 
Signal DataSent : STD_LOGIC := '1'; 
Constant Data : STD_LOGIC_VECTOR(31 downto 0) := X"0030FFF0"; 
Signal Slope : STD_LOGIC := '0'; 
begin 
Prescaler : process(CLK) 
begin 
    if rising_edge(CLK) then 
     if Counter = 5 then 
      Slope <= not(Slope); 
      Counter <= 0; 
     else 
      Counter <= Counter + 1; 
     end if; 
    end if; 
end process; 
SCLK <= SLOPE; 
WriteDac : process(CLK) 
begin 
    if rising_edge(CLK) then 
     if DataSent = '1' then 
      if CurrentBit <= 31 then 
       CSDAC <= '0'; 
       MOSI <= Data(CurrentBit); 
       CurrentBit <= CurrentBit +1; 
      else 
       CSDAC <= '1';  
       DataSent <= '0';     
      end if; 
     end if; 
    end if; 
end process; 
end Behavioral; 

編輯：NEW CODE

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_ARITH.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity DAC is 
    port 
     (
      CLK : in STD_LOGIC;   
      SCLK : out STD_LOGIC; 
      MOSI : out STD_LOGIC; 
      DEBUG : out STD_LOGIC := '1'; 
      CSDAC : out STD_LOGIC := '1'   
     ); 
end DAC; 

architecture Behavioral of DAC is 
Signal Counter : Integer range 0 to 6 := 0; 
Signal Counter2 : Integer range 0 to 33 := 0; 
Signal CurrentBit : Integer range 0 to 33 := 0; 
Signal Fixed : STD_LOGIC := '0'; 
Signal DataSent : STD_LOGIC := '0'; 
Constant Data : STD_LOGIC_VECTOR(31 downto 0) := X"0FFF0C00"; 
Signal Slope_last : STD_LOGIC := '0'; 
Signal Slope : STD_LOGIC := '0'; 
Signal MSS : STD_LOGIC := '0'; 
begin 

WriteDac : process(CLK) 
begin 
    if rising_edge(CLK) then 
     if Counter = 5 then 
      Slope_last <= Slope; 
      Slope <= not(Slope); 
      if Slope_last = '1' and Slope = '0' then 
       if Fixed = '1' then 
        if DataSent = '0' then 
         if CurrentBit <= 31 then 
          CSDAC <= '0'; 
          DEBUG <= '0'; 
          MOSI <= Data(CurrentBit); 
          CurrentBit <= CurrentBit +1; 
         else 
          MOSI <= '0'; 
          CSDAC <= '1'; 
          DEBUG <= '1'; 
          DataSent <= '1'; 
         end if; 
        end if; 
       else 
        if Counter2 <= 31 then 
         CSDAC <= '1'; 
         DEBUG <= '1'; 
         Counter2 <= Counter2 + 1; 
         MSS <= not(MSS); 
         MOSI <= MSS; 
        else 
         Fixed <= '1'; 
         MOSI <= '0'; 
        end if; 
       end if; 
      end if; 
     else 
      Counter <= Counter + 1; 
     end if; 
    end if; 
end process; 
SCLK <= SLOPE; 

end Behavioral; 

我用脈衝MOSI，因爲當我送情侶位SCLK恢復的。首先SCLK運行在約1.4 mhz，當我脈衝mosi它恢復到4.167MHZ注意，1.4mhz左右，它可以是1.5mhz我不記得它太好。

Answer 1

難道你的第二個過程應該對SCLK（或斜率）i.s.o敏感。 CLK？ 有關SPI模塊的一些示例，可以查看opencores.org。即使用Verilog編寫，這也是一個很好的例子，可以做些事情。

Answer 2

您必須更新與SCK相關的位計數器（CurrentBit）。 例如：

... 
WriteDac : process(CLK) 
begin 
    if rising_edge(CLK) then 
     slope_last<=slope; 

     if slope_last='1' and slope='0' then -- e.g. falling edge! 
      if DataSent = '1' then 
...