我是一個模擬工程師,試圖學習VHDL爲我有一個項目。該項目將計算輸入信號的上升沿並將計數預分頻爲較小的數值。例如,如果輸入上有8個計數,則會輸出1個計數。預分頻值可以由用戶改變。我已經成功地完成了prescale部分的工作,但是在目前的情況下,輸出會不斷高漲。VHDL 500納秒脈衝
我想要做的是一旦預分頻計數= =用戶選擇的值,那麼輸出500ns的脈衝而不是恆邏輯高。
我有一個50 MHz的時鐘,所以輸出需要保持25個鎖定週期高,但我不確定如何做到這一點。
任何幫助將是巨大的:)
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
port (
pushbutton: in std_logic;
SW: in std_logic_vector(7 downto 0); -- user select switches
RESET: in std_logic;
OUTPUT: out std_logic;
LEDS: out std_logic_vector(8 downto 0) -- un used leds
);
end counter;
architecture Behavioral of counter is
signal COUNTER: std_logic;
signal PRESCALER: std_logic_vector(7 downto 0);
signal SWITCH: std_logic_vector(7 downto 0);
begin
CounterProcess: process(RESET, pushbutton)
begin
if rising_edge(pushbutton) then
if RESET = '0' then
PRESCALER <= (others => '0');
COUNTER <= '0';
else
if PRESCALER < SWITCH - 1 then
PRESCALER <= PRESCALER + 1;
else
PRESCALER <= (others => '0');
COUNTER <= '1';
end if;
end if;
end if;
end process;
LEDS <= (others => '0'); -- Turn off all unsed LEDs
SWITCH <= SW; -- Asign switch value into a signal
OUTPUT <= COUNTER;
end Behavioral;