VHDL實體端口與組件端口的類型不匹配

Question

我正在使用Xilinx Vivado在VHDL中使用類似MIPS的CPU。我有一個組件，用於我的BranchControl模塊，它是這樣的：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity BranchControl is 
    Port (PL : in STD_LOGIC; 
      BC : in STD_LOGIC_VECTOR(3 downto 0); 
      PC : in STD_LOGIC_VECTOR (31 downto 0); 
      AD : in STD_LOGIC_VECTOR (31 downto 0); 
      Flags : in STD_LOGIC_VECTOR(3 downto 0); 
      PCLoad : out STD_LOGIC; 
      PCValue : out STD_LOGIC_VECTOR (31 downto 0)); 
end BranchControl; 

architecture Behavioral of branchcontrol is 

signal Z,N,P,C,V, T: std_logic; 

begin 

Z <= Flags(3);  -- zero flag 
N <= Flags(2);  -- negative flag 
P <= not N and not Z; -- positive flag 
C <= FLags(1);  -- carry flag 
V <= Flags(0);  -- overflow flag 

T <= 
    '1' when (PL = '1') and (BC = "0000") and (Flags = "XXXX") else -- B 
    '1' when (PL = '1') and (BC = "0010") and (Flags = "1XXX") else -- BEQ 
    '1' when (PL = '1') and (BC = "0011") and (Flags = "0XXX") else -- BNE 
    '1' when (PL = '1') and (BC = "0100") and (Flags = "00XX") else -- BGT 
    '1' when (PL = '1') and (BC = "0101") and (Flags = "11XX") else -- BGE 
    '1' when (PL = '1') and (BC = "0110") and (Flags = "01XX") else -- BLT 
    '1' when (PL = '1') and (BC = "0111") and (Flags = "11XX") else -- BLE 
    '0'; 

with T select 
PCValue <= PC+AD when '1', 
      PC when others; 
PCLoad <= T; 

end Behavioral; 

我寫一個仿真測試BranchControl組件，並確保其工作正常，因爲我打算。這裏是我的模擬：

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 
use IEEE.STD_LOGIC_UNSIGNED.ALL; 

entity SimulBranchControl is 
end SimulBranchControl; 

architecture Behavioral of SimulBranchControl is 

component BranchControl is 
    Port (PL : in STD_LOGIC; 
      BC : in STD_LOGIC_VECTOR(3 downto 0); 
      PC : in STD_LOGIC_VECTOR (31 downto 0); 
      AD : in STD_LOGIC_VECTOR (31 downto 0); 
      Flags : in STD_LOGIC_VECTOR(3 downto 0); 
      PCLoad : out STD_LOGIC; 
      PCValue : out STD_LOGIC_VECTOR (31 downto 0)); 
end component; 

signal iPL : STD_LOGIC; 
signal iBC : STD_LOGIC_VECTOR(3 downto 0); 
signal iPC : STD_LOGIC_VECTOR(31 downto 0); 
signal iAD : STD_LOGIC_VECTOR(31 downto 0); 
signal iFlags : STD_LOGIC_VECTOR(3 downto 0); 

signal clock : std_logic := '0'; 

begin 

    process 
    begin 
     wait for 50 ns; 
     clock <= not clock; 
    end process; 

    process 
    begin 
     wait until clock'event and clock='0'; 
     iPL<='1'; iBC<="0010"; iPC<=x"00000000"; iAD<=x"00000001"; iFlags<="0000"; 

    end process; 

BC0: BranchControl port map(iPL=>PL, iBC=>BC, iPC=>PC, iAD=>AD, iFlags=>Flags); 

end Behavioral; 

出於某種原因，當我嘗試運行Vivado仿真，我得到了闡述步一系列的錯誤：現在

INFO: [VRFC 10-163] Analyzing VHDL file "/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/BranchControl.vhd" into library xil_defaultlib 
INFO: [VRFC 10-307] analyzing entity BranchControl 
INFO: [VRFC 10-163] Analyzing VHDL file "/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd" into library xil_defaultlib 
INFO: [VRFC 10-307] analyzing entity SimulBranchControl 
ERROR: [VRFC 10-719] formal port/generic <ipl> is not declared in <branchcontrol> [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:43] 
ERROR: [VRFC 10-704] formal pl has no actual or default value [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:43] 
ERROR: [VRFC 10-1504] unit behavioral ignored due to previous errors [/home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd:8] 
INFO: [VRFC 10-240] VHDL file /home/meurer/src/acomp/L02/Project2/Project2.srcs/sim_1/new/SimulBranchControl.vhd ignored due to errors 

，從我的理解這意味着我的實體BranchControl和我在仿真中的我的組件具有不兼容的聲明，但我不明白這是如此，它們看起來與我完全一樣。以下是Vivado的screenshot給我的錯誤。

這是怎麼發生的？我究竟做錯了什麼？

Answer 1

實例化中的組件映射是錯誤的方法;它應該是：

bc0: BranchControl port map (pl => ipl, bc => ibc, pc => ipc, ad => iad, flags => iflags);