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我在做一個反應計時器。我以前製作過各個模塊，現在只剩下它們一起使用它們。如何連接我的不同Verilog模塊？
在其他語言中，它們被用作返回值的函數。在這裏我明白模塊是實例化的。我知道如何爲LFSR做實例化，但對於LED多路複用器，我不知道如何實現。
這裏是我的LFSR代碼將被實例化到主模塊：
module LFSR(
input clock,
input reset,
output [29:0] rnd
);
wire feedback = rnd[29]^rnd[5]^rnd[3]^rnd[0];
reg [29:0] random;
always @ (posedge clock or posedge reset)
begin
if (reset)
random <= 30'hF;
else
random <= {random[28:0], feedback};
end
assign rnd = random;
endmodule
這裏是主模塊。在必須調用LED電路的地方顯示「Hi」，然後再顯示秒錶。我用評論標記了他們。我該怎麼做？
module reaction(
input clock,
input reset,
input start,
input stop,
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output h,
output dp,
output led
);
reg [29:0] random;
LFSR random_gen(.clock(clock), .reset(reset), .rnd(random));
localparam [1:0]
idle = 2'b00,
start = 2'b01,
time_it = 2'b10,
stop = 2'b11;
reg state_reg, state_next;
reg [29:0] count_reg, count_next;
always @ (posedge clock or posedge reset)
begin
if(reset)
begin
state_reg <= idle;
count_reg <= 0;
end
else
state_reg <= state_next;
count_reg <= count_next;
end
always @ (*)
begin
state_next = state_reg; //default state stays the same
count_next = count_reg;
case(state_reg)
idle:
//"DISPLAY HI HERE .......... HOW??
if(start)
begin
count_next = random;
state_next = start;
end
start:
if(count_next == 750000000) // 750M equals a delay of 15 seconds.
begin
led = 1'b1;
state_next = time_it;
end
else
count_next = count_reg + 1;
time_it:
//START STOPWATCH????????
現在我已經做了一個工作秒錶。它寫如下：
module stopwatch(
input clock,
input reset,
input start,
output a, b, c, d, e, f, g, dp,
output [3:0] an
);
reg [3:0] reg_d0, reg_d1, reg_d2, reg_d3; //registers that will hold the individual counts
reg [22:0] ticker; //23 bits needed to count up to 5M bits
wire click;
//the mod 5M clock to generate a tick ever 0.1 second
always @ (posedge clock or posedge reset)
begin
if(reset)
ticker <= 0;
else if(ticker == 5000000) //if it reaches the desired max value reset it
ticker <= 0;
else if(start) //only start if the input is set high
ticker <= ticker + 1;
end
assign click = ((ticker == 5000000)?1'b1:1'b0); //click to be assigned high every 0.1 second
always @ (posedge clock or posedge reset)
begin
if (reset)
begin
reg_d0 <= 0;
reg_d1 <= 0;
reg_d2 <= 0;
reg_d3 <= 0;
end
else if (click) //increment at every click
begin
if(reg_d0 == 9) //xxx9 - the 0.1 second digit
begin //if_1
reg_d0 <= 0;
if (reg_d1 == 9) //xx99
begin // if_2
reg_d1 <= 0;
if (reg_d2 == 5) //x599 - the two digit seconds digits
begin //if_3
reg_d2 <= 0;
if(reg_d3 == 9) //9599 - The minute digit
reg_d3 <= 0;
else
reg_d3 <= reg_d3 + 1;
end
else //else_3
reg_d2 <= reg_d2 + 1;
end
else //else_2
reg_d1 <= reg_d1 + 1;
end
else //else_1
reg_d0 <= reg_d0 + 1;
end
end
//The Circuit for Multiplexing - Look at my other post for details on this
localparam N = 18;
reg [N-1:0]count;
always @ (posedge clock or posedge reset)
begin
if (reset)
count <= 0;
else
count <= count + 1;
end
reg [6:0]sseg;
reg [3:0]an_temp;
reg reg_dp;
always @ (*)
begin
case(count[N-1:N-2])
2'b00 :
begin
sseg = reg_d0;
an_temp = 4'b1110;
reg_dp = 1'b1;
end
2'b01:
begin
sseg = reg_d1;
an_temp = 4'b1101;
reg_dp = 1'b0;
end
2'b10:
begin
sseg = reg_d2;
an_temp = 4'b1011;
reg_dp = 1'b1;
end
2'b11:
begin
sseg = reg_d3;
an_temp = 4'b0111;
reg_dp = 1'b0;
end
endcase
end
assign an = an_temp;
reg [6:0] sseg_temp;
always @ (*)
begin
case(sseg)
4'd0 : sseg_temp = 7'b1000000;
4'd1 : sseg_temp = 7'b1111001;
4'd2 : sseg_temp = 7'b0100100;
4'd3 : sseg_temp = 7'b0110000;
4'd4 : sseg_temp = 7'b0011001;
4'd5 : sseg_temp = 7'b0010010;
4'd6 : sseg_temp = 7'b0000010;
4'd7 : sseg_temp = 7'b1111000;
4'd8 : sseg_temp = 7'b0000000;
4'd9 : sseg_temp = 7'b0010000;
default : sseg_temp = 7'b0111111; //dash
endcase
end
assign {g, f, e, d, c, b, a} = sseg_temp;
assign dp = reg_dp;
endmodule
我希望我能夠解釋我的問題。
感謝您閱讀
更新代碼：
module reaction(
input clock,
input reset,
input start,
input stop,
output a,
output b,
output c,
output d,
output e,
output f,
output g,
output dp,
output [3:0] an,
output reg led
);
wire [29:0] random;
reg go_hi, go_start;
//instantiate the random number generator
LFSR random_gen(.clock(clock), .reset(reset), .rnd(random));
//inistantiate module to display hi
say_hi sayhi(.clock(clock), .reset(reset), .go(go_hi), .a(a), .b(b), .c(c), .d(d),
.e(e), .f(f), .g(g), .dp(dp), .an(an));
//instantiate the millisecond timer
stopwatch timer(.clock(clock), .reset(reset), .start(go_start), .a(a), .b(b), .c(c), .d(d),
.e(e), .f(f), .g(g), .dp(dp), .an(an));
localparam [1:0]
idle = 2'b00,
starting = 2'b01,
time_it = 2'b10;
//stop = 2'b11;
reg state_reg, state_next;
reg [29:0] count_reg, count_next;
always @ (posedge clock or posedge reset)
begin
if(reset)
begin
state_reg <= idle;
count_reg <= 0;
end
else
state_reg <= state_next;
count_reg <= count_next;
end
always @ (*)
begin
state_next = state_reg; //default state stays the same
count_next = count_reg;
case(state_reg)
idle:
begin
//DISPLAY HI HERE
go_hi = 1;
if(start)
begin
go_hi = 0; //dont display hi anymore
count_next = random;
state_next = starting;
end
end
starting:
begin
if(count_next == 750) // 750M equals a delay of 15 seconds.
begin //and starting from 'rand' ensures a random delay
led = 1'b1;
state_next = time_it;
end
else
count_next = count_reg + 1;
end
time_it:
begin
go_start = 1;
if(stop)
go_start = 0;
end
endcase
end
endmodule
相關：http://stackoverflow.com/questions/1704989/wiring-two-modules-in-verilog –