的Verilog連接2個模塊

Question

我有設計一個JK觸發器這樣，

module jk_flip_flop(input pr,input clr,input j,input k,input clock,output reg q,output qNot); 
assign qNot = (pr == 0 & clr == 0)?1:~q; 
always @ (posedge clock or negedge clock) 
    begin 
     if(pr != 1 || clr != 1)begin 
      case ({pr, clr}) 
       2'b01: q<=1'b1; 
       2'b10: q<=1'b0; 
       2'b00: q<=1'b1; 
      endcase 
     end 
     else if(pr == 1 & clr == 1) begin 
      case ({j, k}) 
      2'b00: q <= q; 
      2'b01: q<=1'b0; 
      2'b10: q<=1'b1; 
      endcase 
     end 
     if(pr == 1 & clr == 1 & j == 1 & k == 1 & clock == 1) 
      q <= ~q; 
    end 
endmodule 

我想通過5計數器實現divede，我需要使用三個JK觸發器要做到這一點，我應該如何使用一遍又一遍這個模塊，我的意思是我應該怎麼以前觸發器的輸出連接到下一個

Answer 1

事情是這樣的：

module something (input A, input B, output C) 
... 
endmodule 

wire same_wire; 
wire input_wire, output_wire; 
wire middle_wire; 

something some1(.A(same_wire), .B(input_wire), .C(middle_wire)); 
something some2(.A(same_wire), .B(middle_wire), .C(output_wire)); 
...