VHDL時鐘序列Q3

Question

我必須創建一個VHDL序列，只需要一個時鐘輸入，並把5 led的序列see picture 我正確的思想，使用std_logic_vector我可以然後連接每個向量輸出到單個LED爲了創建這個序列或者我想念解釋使用std_logic_vector？

我已經使用的代碼是

library ieee; 
use ieee.std_logic_1164.all; 
use ieee.std_logic_unsigned.all; 
use ieee.numeric_std.all; -- i have used this package as my CLK-CNT signal counts in integer format rather than binary and i am performing an ADD sum of the CLK_CNT 


entity REG_LED is 
PORT(CLK:  IN std_logic;    -- CLK input 
    LEDS:  Out std_logic_vector (4 downto 0)); -- initialise output 
End REG_LED; 

ARCHITECTURE behavioral OF REG_LED IS 
SIGNAL CLK_CNT:  integer range 0 to 9:= 0; -- initailise comparison signal used for counting clock pulses. 
-- This signal will be used by the program to recognise where in the sequnce the program is and thus determine the next state required for the sequence. 
BEGIN 

    CLK_Process: PROCESS (CLK) -- begin the CLK_CNT Process 
    BEGIN 

    if rising_edge(CLK) Then 
     if CLK_CNT = 8 then 
      CLK_CNT <= 0; -- this resets the clock pulse count to 0 
     else 
      CLK_CNT <= CLK_CNT + 1 ; -- used to count each clock pulse upto the reset 
     End if; 
-- this process has been kept seperate to the LED output process in order to isolate the event from the output process and limit the possiblities of errors   
    END IF; 

    END PROCESS ; 

    LED_PROCESS: Process (CLK_CNT) -- LED Outputs based on Temp count 

    BEGIN -- begin the output sequence 

     Case CLK_CNT is 
-- i use a case statement to compare the value of the CLK_CNT signal and produce the required LEDS output 
-- this ensures the 
      When 0 => 
       LEDS <= "11111"; -- S0 when clock count is 0 
      When 1 => 
       LEDS <= "00001"; -- S1 when clock count is 1 
      When 2 =>  
       LEDS <= "00001"; -- S2 when clock count is 2 
      When 3 => 
       LEDS <= "11111"; -- S3 when clock count is 3 
      When 4 => 
       LEDS <= "00000"; -- S4 when clock count is 4 
      When 5 => 
       LEDS <= "11111"; -- S5 when clock count is 5 
      When 6 => 
       LEDS <= "00100"; -- S6 when clock count is 6 
      When 7 => 
       LEDS <= "01010"; -- S7 when clock count is 7 
      When 8 => 
       LEDS <= "10001"; -- S8 when clock count is 8 this is the final clock count state 

      When others => 
       LEDS <= "11111"; -- Restart Sequence 

     End Case;    

    End Process; 
END behavioral; 

我已經模擬波形和其產生所要求的序列，但是可以將此輸出beused驅動5個不同的發光二極管，或者它也只是一個5 5個輸出位字是一個端口的輸出？即時通訊新的VHDL，所以任何幫助，將不勝感激

Answer 1

你的代碼看起來很好，如果你的模擬表明它正在根據你需要什麼功能，那麼你幾乎是好去。

A std_logic_vector確實是一些電線（巴士）。你必須考慮它的物理意義，因爲這是編程FPGA時真正發生的事情。所以是的，你可以將公共汽車分成（或分出）單獨的線路。這可以這樣完成：

signal LED_LINE_0 : std_logic; 
signal LED_LINE_1 : std_logic; 
LED_LINE_0 <= LEDS(0); 
LED_LINE_1 <= LEDS(1); 

...等等。這一次撕掉了一根電線。您也可以通過一次拆下多根電線將公共汽車分成小型公交車。例如

signal small_bus_1 : std_logic_vector(1 downto 0); 
signal small_bus_2 : std_logic_vector(1 downto 0); 
signal big_bus : std_logic_vector(3 downto 0); 

small_bus_1 <= big_bus(3 downto 2); 
small_bus_2 <= big_bus(1 downto 0); 

然後，您可以在您的約束文件寫入（或使用GUI在您的FPGA品牌IDE）指定您希望這些std_logic被分配到其中一個引腳上的FPGA（即驅動器你需要的LED）。