在VHDL中進行波形仿真時忽略時鐘輸入？

Question

我是硬件描述語言理論和VHDL新手。我需要用VHDL設計一個2421加計數器。我使用T觸發器構建了一個同步二進制向上計數器，並通過激活預設並有條件地清除，將其修改爲生成最後2個期望的8和9的計數。當我嘗試波形模擬時，時鐘輸入被忽略。無法弄清楚問題所在。下面是代碼：

library ieee; 
use ieee.std_logic_1164.all; 
entity count2421 is  
port(clock:in std_logic;qq:buffer std_logic_vector(3 downto 0)); 
end count2421; 
architecture arch of count2421 is 
component t_ff is 
port(clock,clear,preset,t:in std_logic;q:buffer std_logic); 
end component; 
signal p1,p2,p,t,u,a,b:std_logic; 
begin 
    t<='1'; 
    u<='0'; 
    qq(0)<='0'; 
    qq(1)<='0'; 
    qq(2)<='0'; 
    qq(3)<='0'; 
    process(clock) begin 
     if(clock'event and clock='0') then 
      p1<=(not qq(3)) and qq(2) and qq(1) and qq(0); 
      p2<=qq(3) and qq(2) and qq(1) and (not qq(0)); 
      p<=p1 or p2; 
      a<=qq(3) and qq(2); 
      b<=a and qq(1); 
     end if; 
    end process; 
    stage0:t_ff port map(clock,u,p,t,qq(0)); 
    stage1:t_ff port map(clock,u,p,qq(0),qq(1)); 
    stage2:t_ff port map(clock,u,p,a,qq(2)); 
    stage3:t_ff port map(clock,p1,p2,b,qq(3)); 
end arch; 

這裏是T觸發器代碼：

library ieee; 
    use ieee.std_logic_1164.all; 
    entity t_ff is 
    port(clock,clear,preset,t:in std_logic;q:buffer std_logic); 
    end t_ff; 
    architecture arch of t_ff is 
signal temp:std_logic; 
begin 
    temp<=q; 
    process(clock) 
    begin 
     if(clock'event and clock='0') then 
      if(clear='1') then 
       q<='0'; 
      elsif(preset='1') then 
       q<='1'; 
      elsif(t='1') then 
       q<=not q; 
      end if; 
     end if; 
    end process; 
end arch; 

Answer 1

緩衝港QQ有兩個驅動程序。 解決之前，先擔心其他事情。