XILINX ISE將I/O標記設置爲時鐘

我在Xilinx ISE IDE上並使用原理圖編輯器。XILINX ISE將I/O標記設置爲時鐘

（點擊新窗口）

約束文件如下：

NET "A" LOC = M18; 
NET "F" LOC = P15; 
NET "B" LOC = M16; 


NET "A" PULLUP; 
NET "B" PULLUP; 
NET "F" DRIVE = 8;

但是，當我想編譯我的程序，有這樣的錯誤：

ERROR:Place:1108 - A clock IOB/BUFGMUX clock component pair have been found 
    that are not placed at an optimal clock IOB/BUFGMUX site pair. The clock 
    IOB component <B> is placed at site <M16>. The corresponding BUFG component 
    <B_BUFGP/BUFG> is placed at site <BUFGMUX_X2Y3>. There is only a select set 
    of IOBs that can use the fast path to the Clocker buffer, and they are not 
    being used. You may want to analyze why this problem exists and correct it. 
    If this sub optimal condition is acceptable for this design, you may use the 
    CLOCK_DEDICATED_ROUTE constraint in the .ucf file to demote this message to a 
    WARNING and allow your design to continue. However, the use of this override 
    is highly discouraged as it may lead to very poor timing results. It is 
    recommended that this error condition be corrected in the design. A list of 
    all the COMP.PINs used in this clock placement rule is listed below. These 
    examples can be used directly in the .ucf file to override this clock rule. 
    < NET "B" CLOCK_DEDICATED_ROUTE = FALSE; > 
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

如何解決它？

來源

2015-07-19 Martin Fischer

你的FPGA板名是什麼？你的時鐘引腳位置不是最佳的。 – Paebbels

雖然理論上任何信號都可以用作時鐘，但FPGA並非如此;至少不是最佳的。時鐘需要特殊的注意事項，以轉換爲限制FPGA的哪個引腳可以路由到時鐘網絡。

我懷疑在你的情況下，你使用了一個按鈕來充當一個時鐘信號，它只會在一個非常小的設計（比如你的）上工作，因爲它的反彈和它不是一個時鐘使能輸入端口。

你可以告訴你想要的次優和潛在錯誤的時鐘路徑中加入以下約束你的.UCF工具：

NET "B" CLOCK_DEDICATED_ROUTE = FALSE;

請記住，你不應該這樣做而不確定你的設計沒問題......我建議你用連接到FPGA時鐘端口的「真實」時鐘進行進一步的設計，每塊電路板都有一個。這種限制會讓你的設計工作，但是更大更快的設計很可能成爲問題的根源。

來源

2015-07-19 13:37:04

XILINX ISE將I/O標記設置爲時鐘

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