VHDL-變量的使用

我是VHDL的新手。這是一個劃分代碼。VHDL-變量的使用

library ieee; 
    USE ieee.std_logic_1164.all; 
    USE ieee.std_logic_unsigned.all; 
    use IEEE.numeric_std.all; 

entity division3 is 
    port(num1, num2 : in std_logic_vector(7 DOWNTO 0); 
    quotient : out std_logic_vector(15 DOWNTO 0)); 
    end division3; 

    architecture arch_div3 of division3 is 
    variable n_times: integer:=1; 
      signal v_TEST_VARIABLE1 : integer; 
      signal v_TEST_VARIABLE2 : integer; 
        begin 
     P3: PROCESS(num1, num2) 
     begin 

     if(num1>num2) then 
     v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ; 
     v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ; 
     L1:loop 
     n_times := n_times + 1; 
     exit when (v_TEST_VARIABLE2 - v_TEST_VARIABLE1)>0 
     v_TEST_VARIABLE1 <= v_TEST_VARIABLE1 - v_TEST_VARIABLE2; 
     end loop L1; 


    quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length)); 

    elsif (num2>num1) then 
     v_TEST_VARIABLE1 <= to_integer(unsigned(num1)) ; 
     v_TEST_VARIABLE2 <= to_integer(unsigned(num2)) ; 
     L2:loop 
     n_times:=n_times+1; 
     exit when (v_TEST_VARIABLE1 - v_TEST_VARIABLE2)>0 
     v_TEST_VARIABLE2 <= v_TEST_VARIABLE2 - v_TEST_VARIABLE1; 

    quotient <= std_logic_vector(to_unsigned(n_times-1,quotient'length)); 


    else 
     quotient <= x"0001"; 
    end if; 

    end PROCESS P3; 
    end arch_div3;

我在編譯時遇到錯誤。

** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(25): Physical unit hidden by declaration of 'v_test_variable1' at line 13. 
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(25): near "<=": expecting ';' 
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(37): Physical unit hidden by declaration of 'v_test_variable2' at line 14. 
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(37): near "<=": expecting ';' 
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(42): near "else": expecting "END" 
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(12): Variable declaration 'n_times' not allowed in this region. 
** Error: C:/Actel/Libero_v9.1/Model/division3.vhd(47): VHDL Compiler exiting

我對信號和變量的使用很不清楚。我認爲這是我搞亂的地方。有人可以幫我嗎？在此先感謝。對於相同的代碼測試平臺 -

LIBRARY ieee; 
USE ieee.std_logic_1164.ALL; 
use IEEE.numeric_std.all; 


ENTITY division3_tb IS 
END division3_tb; 

ARCHITECTURE behavior OF division3_tb IS 

    COMPONENT test --'test' is the name of the module needed to be tested. 

    port(num1, num2 : in std_logic_vector(7 DOWNTO 0); 
    quotient : out std_logic_vector(15 DOWNTO 0)); 

    END COMPONENT; 

    signal num1 : std_logic_vector := "00000000"; 
    signal num2 : std_logic_vector := "00000000"; 

    signal quotient : std_logic_vector(15 downto 0); 

    constant clk_period : time := 1 ns; 
BEGIN 

    uut: test PORT MAP (
     num1 => num1, 
      num2 => num2, 
      quotient => quotient 
     );  


    clk_process :process 
    begin 
     num1 <= "00001000"; 
     wait for clk_period/2; --for 0.5 ns signal is '0'. 
     num1 <= "00001110"; 
     wait for clk_period/2; --for next 0.5 ns signal is '1'. 
    end process; 

    stim_proc: process 
    begin   
     wait for 7 ns; 
     num2 <="00000001"; 
     wait for 3 ns; 
     num2 <="00000010"; 
     wait for 17 ns; 
     num2 <= "00000011"; 
     wait for 1 ns; 
     num2 <= "00000110"; 
     wait; 
    end process; 

END;

它說：在編譯

** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(19): Array type for 'num1' is not constrained. 
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(20): Array type for 'num2' is not constrained. 
** Error: C:/Actel/Libero_v9.1/Model/division3_tb.vhd(55): VHDL Compiler exiting

。我如何在測試平臺中實例化？

來源

2014-06-18 Mojo Jojo

的Error: ...: Physical unit hidden by declaration of ...是由於在exit when ...語句，由此代碼是的解釋爲端缺乏 ;：

exit when ... > 0 v_TEST_VARIABLE1 ...

所以表達式看起來像一個物理值與單元v_TEST_VARIABLE1，因此錯誤信息。

其他一些VHDL相關評論的代碼：

end loop L2;是quotient <=前失蹤。因爲 ieee.std_logic_unsigned不是VHDL IEEE標準包。
可變n_times應的過程中被聲明，而不是在架構，因爲可變使用是本地的過程中，和（共享）體系結構中的聲明的變量通常是用於測試臺使用。
過程變量n_times必須在過程的開始時初始化，以使初始化在每次計算中都生效。聲明中的初始值僅適用於第一次進程運行。
分配到信號v_TEST_VARIABLE1和v_TEST_VARIABLE2與<= 不會生效直到增量週期後，使新的值是不迭代，它看起來像在代碼的意圖期間可用。將v_TEST_VARIABLE1和v_TEST_VARIABLE2更改爲過程變量，和使用:=進行分配。
與loop .. exit when ... end loop構造並不合成的，由於退出條件取決於運行時間值，從而不能在合成時確定用於創建電路。考慮將算法更改爲使用固定數量的循環與for ...。
請記住做一個測試臺來測試算法的正確性。這也將允許您優化代碼，並通過簡單的更新代碼測試。

來源

2014-06-18 11:04:19

非常感謝Morten。作品..！ :) –

VHDL-變量的使用

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