2016-03-23 36 views
0

我正在寫一個進程,必須尋找每一個傳入位,跟蹤接收或不接收的總數是1,並且,當時間到了必須比較該值爲參考值。該過程如下:信號下降到未定義,而所有相關的信號被定義

parity_tester : process(clk, sub_rst, barrel_data_in, barrel_enable, parity_test, parity_ref) 
     variable last_known_enable  : boolean := false; 
     variable last_known_data  : STD_LOGIC := '0'; 
     variable parity_error_out  : STD_LOGIC := '0'; 
     variable parity_ref_reg   : STD_LOGIC := '0'; 
     variable even     : STD_LOGIC := '1'; 
    begin 
     if sub_rst then 
      last_known_enable := false; 
      last_known_data  := '0'; 
      parity_error_out := '0'; 
      even    := '1'; 
     elsif rising_edge(clk) then 
      if barrel_enable then 
       last_known_enable := true; 
       last_known_data  := barrel_data_in; 
      else 
       if last_known_enable then 
        last_known_enable := false; 
        if last_known_data = '1' then 
         even := not even; 
        end if; 
       end if; 
      end if; 

      if parity_test then 
       case parity_bit_in_type is 
        when 0 => 
         parity_error_out := even xnor parity_ref; 
        when 1 => 
         parity_error_out := even xor parity_ref; 
        when 2 => 
         parity_error_out := parity_ref; 
        when 3 => 
         parity_error_out := not parity_ref; 
        when others => 
         parity_error_out := '1'; 
       end case; 
      end if; 
     end if; 
     parity_error <= parity_error_out; 
    end process; 

在這裏,我遇到一個問題:由於在這個過程中靈敏度列表中定義的所有信號被定義,但根據GHDL(模擬器)的值變爲不確定的每當parity_test變爲真: Signals 我在做什麼錯?

我刪除了這裏因爲當我改變到我的筆記本電腦,錯誤改變了:它關於案件開關。我仍然不明白爲什麼。 parity_bit_in_type是一個範圍(0到3)的通用Natural。如果我拿出我需要的語句(在這種情況下爲0)並刪除案例,所有事情都按預期工作。 WebPack ISE似乎沒有抱怨,所以它開始感覺像GHDL中的錯誤。

GHDL版本:

/Downloads/ghdl-gcc-git » ghdl --version 
GHDL 0.34dev (20151126) [Dunoon edition] 
Compiled with GNAT Version: 5.3.0 
mcode code generator 
Written by Tristan Gingold. 

Copyright (C) 2003 - 2015 Tristan Gingold. 
GHDL is free software, covered by the GNU General Public License. There is NO 
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 

一個最小的例子顯示了相同的行爲

library IEEE; 
use IEEE.STD_LOGIC_1164.ALL; 

entity uart_receiv_parity is 
    generic (
     parity_bit_in_type  : Natural range 0 to 3 
    ); 
    port (
     rst      : in boolean; 
     clk      : in STD_LOGIC; 
     parity_error   : out STD_LOGIC -- Signals that the parity check has failed, is zero if there was none 
    ); 
end entity; 

architecture Behavioral of uart_receiv_parity is 
begin 
    parity_tester : process(clk, rst) 
     variable parity_error_out  : STD_LOGIC := '0'; 
    begin 
     if rst then 
      parity_error_out := '0'; 
     elsif rising_edge(clk) then 
      case parity_bit_in_type is 
       when 0 => 
        parity_error_out := '1'; 
       when 1 => 
        parity_error_out := '0'; 
       when 2 => 
        parity_error_out := '1'; 
       when 3 => 
        parity_error_out := '0'; 
       when others => 
        parity_error_out := '1'; 
      end case; 
     end if; 
     parity_error <= parity_error_out; 
    end process; 
end Behavioral; 
+0

不,我不知道。另一個好奇的是,如果我更改爲parity_error_out:= even,那麼這個未定義的事情就不會再發生了。 – Cheiron

+0

什麼是GHDL版本和後端?紅色區域依賴於輸入數據的時間是多少?紅色值是'U'還是'X'? – Paebbels

+0

將進程置於新體系結構中並對其應用刺激時,錯誤仍然會發生嗎? –

回答

0

所以,這是我的錯畢竟:在測試平臺的信號是從兩個源驅動。因此'1'導致信號被'1'和'0'驅動,導致'x'。當信號應該是'0'時,輸出實際上是零。