簡單VHDL 4比1個MUX測試平臺吊

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-----------begin part1.vhdl--------------------- 


library ieee; 
use ieee.std_logic_1164.all; 

entity part1 is 
    generic (width : integer :=7); 
    PORT(a, b, c, d: IN std_logic_vector(width downto 0); 
     sel: IN std_logic_vector(1 downto 0); 
     result: OUT std_logic_vector(width downto 0) 
    ); 
end part1; 

architecture muxbehav of part1 is 

BEGIN 

    result <=  a after 5 ns when sel="00" else 
        b after 5 ns when sel="01" else 
        c after 5 ns when sel="10" else 
        d after 5 ns; 
end muxbehav; 

-----------end part1.vhdl--------------------- 

    -----------begin part1_tb.vhdl------------------ 

library ieee; 
use ieee.std_logic_1164.all; 


entity part1_tb is 
    generic(width : integer := 7); 
end part1_tb; 

architecture tb of part1_tb is 

    signal t_a: std_logic_vector(width downto 0):="00000000"; 
    signal t_b: std_logic_vector(width downto 0):="00000000"; 
    signal t_c: std_logic_vector(width downto 0):="00000000"; 
    signal t_d: std_logic_vector(width downto 0):="00000000"; 
    signal t_s: std_logic_vector(1 downto 0); 
    signal t_o: std_logic_vector(width downto 0); 

component part1 
    generic(width : integer); 
    PORT(a, b, c, d: IN std_logic_vector(width downto 0); 
     sel: IN std_logic_vector(1 downto 0); 
     result: OUT std_logic_vector(width downto 0) 
    ); 
    end component; 

    begin 

    U_part1: part1 generic map(width) port map(a=>t_a, b=>t_b, c=>t_c, d=>t_d, sel=>t_s, result=>t_o); 

    process 

     begin 

     t_a <= "11111111"; 
     t_b <= "00000001"; 
     t_c <= "10101010"; 
     t_d <= "01010101"; 

     wait for 10 ns; 
     t_s <= "00"; 
     wait for 6 ns; 
     assert (t_o="11111111") report "Error input a" severity error; 

     wait for 10 ns; 
     t_s <= "01"; 
     wait for 6 ns; 
     assert (t_o="00000001") report "Error input b" severity error; 

     wait for 10 ns; 
     t_s <= "10"; 
     wait for 6 ns; 
     assert (t_o="10101010") report "Error input c" severity error; 

     wait for 10 ns; 
     t_s <= "11"; 
     wait for 6 ns; 
     assert (t_o="01010101") report "Error input d" severity error; 

     wait; 

    end process; 
end tb; 

-----------end part1_tb.vhdl------------------

你好，這是我寫的VHDL我的第一個代碼。這是一個簡單的4至1 MUX，可以接受任何寬度的矢量。但是，當我嘗試運行我的測試平臺時，GHDL只是掛起。我已經看過類似於我的測試平臺，但我仍然無法找到我爲什麼掛着。有任何想法嗎？簡單VHDL 4比1個MUX測試平臺吊

來源

2011-03-15 Drew

「掛起」，你的意思是模擬運行沒有發生任何事情，或者模擬時間停止前進？ – 2011-03-15 08:01:38

您可以發佈您的平臺的詳細信息和版本GHDL的？和你的編譯/運行命令？ – 2011-03-15 21:22:01

什麼是「等待」的過程做的結束？它迫使它停止嗎？對不起，我不知道VHDL那麼好..更多的Verilog人。 – user623879 2011-03-15 00:46:31

嗯。我看不出有任何理由讓它掛起。

我剛剛在Ubuntu 10.04的ghdl0.29上試過了你的代碼 - 對我來說工作正常（因爲它沒有打印任何消息而退出，所以它看起來就像你的代碼工作:)在gtkwave中波浪看起來也令人信服。

你可以嘗試刪除你的文件夾work和可執行文件並重新編譯？

對不起，這不是真的，讓你邁出的答案！

來源

2011-03-15 21:21:31

簡單VHDL 4比1個MUX測試平臺吊

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