我剛剛寫了一個VHDL代碼,但它無法正常工作。我想用D觸發器編寫一個不穩定的計數器,計數如下:0 –> 13 –> 5 –> 7 –> 12 –> 6 –> 3 –> 15 –> 10 -> 0
。 它應具有以下屬性:不穩定的計數器代碼通過VHDL
- 它應該是結構
- 四個輸出端(3下降到0)
- 它應該有一個異步復位
- 它應該有一個使能
- 它應該有一個活躍的高時鐘。
我在下面寫了我的代碼,但是我知道它不好。任何人都可以幫助我嗎?
library IEEE ;
use IEEE.std_logic_1164.all ;
-- and_gate
entity and_gate is
port(Input1, Input2:in bit;
Output:out bit);
end and_gate;
architecture behavioral of and_gate is
begin
Output <= (Input1 and Input2) ;
end behavioral;
-- or_gate
entity or_gate is
port(Input1, Input2:in bit;
Output:out bit);
end or_gate;
architecture behavioral of or_gate is
begin
Output <= (Input1 or Input2);
end behavioral;
-- not_gate
entity not_gate is
port(Input : in bit; Output : out bit);
end not_gate;
architecture behavioral of not_gate is
begin
Output <= not(Input);
end behavioral;
-- D-FF
entity DFF is
port(CLK,RESET,EN,DIN :in bit;
COUNT :out bit);
end DFF;
architecture behavioral of DFF is
begin
LSEQ :process(RESET,CLK)
begin
if(RESET ='0')then
COUNT <='0';
elsif(CLK'event and CLK ='1')then
if(EN ='1')then
COUNT <=DIN;
end if;
end if;
end process;
end behavioral;
-- counter
entity counter is
port (CLK,RESET,EN: in bit;
COUNT : out bit_vector(3 downto 0));
end counter;
architecture counter_structural of counter is
component and_gate
port(Input1,Input2 : in bit; Output: out bit);
end component;
component or_gate
port(Input1,Input2 : in bit; Output : out bit);
end component;
component not_gate
port(Input : in bit; Output : out bit);
end component;
component DFF
port(CLK,RESET,EN,DIN :in bit; COUNT :out bit);
end component;
signal A,B,C,D,ai,bi,ci,a1,a2,a3,a4,a5,a6,a7,a8,a9,a10,a11,a12,a13,a14,a15 : bit;
begin
Gate1: not_gate port map (A,ai);
Gate2: not_gate port map (B,bi);
Gate3: and_gate port map (ai,bi,a1);
Gate4: and_gate port map (C,D,a2);
Gate5: or_gate port map (a1,a2,a3);
Gate6: DFF port map (CLK,RESET,EN,a3,COUNT(0));
Gate7: and_gate port map (ai,B,a4);
Gate8: not_gate port map (c,ci);
Gate9: and_gate port map (ai,D,a5);
Gate10: or_gate port map (a4,ci,a6);
Gate11: or_gate port map (a5,a6,a7);
Gate12: DFF port map (CLK,RESET,EN,a7,COUNT(1));
Gate13: and_gate port map (A,B,a8);
Gate14: and_gate port map (C,D,a9);
Gate15: or_gate port map (a8,a9,a10);
Gate16: DFF port map (CLK,RESET,EN,a10,COUNT(2));
Gate17: and_gate port map (ai,B,a11);
Gate18: and_gate port map (ci,D,a12);
Gate19: and_gate port map (ai,D,a13);
Gate20: or_gate port map (a11,a12,a14);
Gate21: or_gate port map (a13,a14,a15);
Gate22: DFF port map (CLK,RESET,EN,a15,COUNT(3));
end counter_structural ;
[最小,完整和可驗證示例]的一部分(https://stackoverflow.com/help/mcve)已完成 - 重現問題和驗證所需的所有信息 - 「不起作用」不是問題陳述。什麼是不正確的? (它在做什麼?)你有測試臺嗎?計數順序是否需要? – user1155120
請包括這個結構的原理圖。基於這段代碼,它看起來像是一堆連接着我的門。 – JHBonarius