-1
我使用下面的代碼的第一位向上計數器。 我已經做了必要的端口映射,我沒有語法錯誤。雖然我的模擬不起作用。模擬錯誤在vhdl
entity ZeroBit is
Port (inbit0 : in STD_LOGIC;
Load : in STD_LOGIC;
Q0 : out STD_LOGIC;
En : in STD_LOGIC;
reset : in STD_LOGIC;
Clk : in STD_LOGIC;
UpDown : in STD_LOGIC);
end ZeroBit;
architecture Behavioral of ZeroBit is
component D_FlipFlop
Port (Din : in STD_LOGIC;
En : in STD_LOGIC;
Q : out STD_LOGIC;
reset : in STD_LOGIC;
Clk : in STD_LOGIC);
end component;
component andGate
Port (A : in STD_LOGIC;
B : in STD_LOGIC;
F : out STD_LOGIC);
end component;
component orGate
Port (A : in STD_LOGIC;
B : in STD_LOGIC;
F : out STD_LOGIC);
end component;
component notGate
Port (in0 : in STD_LOGIC;
out0 : out STD_LOGIC);
end component;
component Mux4x1
Port (C0 : in STD_LOGIC;
C1 : in STD_LOGIC;
X0 : in STD_LOGIC;
X1 : in STD_LOGIC;
X2 : in STD_LOGIC;
X3 : in STD_LOGIC;
M : out STD_LOGIC);
end component;
signal muxout, inmux0, inmux1, orout, andout0, andout1, notUpDown : std_logic;
begin
FF0 : D_FlipFlop
port map (Din => muxout,
En => '1',
Q => inmux0,
reset => reset,
Clk => Clk);
Mux0 : Mux4x1
port map(C0 => orout,
C1 => Load,
X0 => inmux0,
X1 => inmux1,
X2 => inbit0,
X3 => inbit0,
M => muxout);
notG : notGate
port map(in0 => UpDown,
out0 => notUpDown);
and0 : andGate
port map(A => En,
B => notUpDown,
F => andOut0);
and1 : andGate
port map(A => En,
B => UpDown,
F => andOut1);
orG : orGate
port map(A => andOut0,
B => andOut1,
F => orout);
Q0 <= inmux0;
end Behavioral;
這裏沒有問題。但是:提示:您可以將內部信號添加到波形窗口並重新運行SIM,這可以讓您識別未按期望的方式發生的事情。然後你必須找出原因並加以解決。 –
@BrianDrummond是的你是對的,我無法想象發生了什麼問題..感謝您的建議.. –
看看你的信號在內部,特別是'inmux1'。 – PlayDough